Semiconductor device manufacturing: process – With measuring or testing – Electrical characteristic sensed
Reexamination Certificate
2005-10-18
2005-10-18
Whitehead, Jr., Carl (Department: 2813)
Semiconductor device manufacturing: process
With measuring or testing
Electrical characteristic sensed
C438S149000, C438S157000, C438S479000, C438S652000
Reexamination Certificate
active
06955932
ABSTRACT:
Several methods and structures are disclosed for determining electrical properties of silicon-on-insulator (SOI) wafers and alternate versions of such wafers such as strained silicon:silicon/germanium:-on-insulator (SSGOI) wafers. The analyzed electrical properties include mobilities, interface state densities, and oxide charge by depositing electrodes on the wafer surface and measuring the current-voltage behavior using these electrodes. In a single gate structure, the source and drain electrodes reside on the wafer surface and the buried insulator acts as the gate oxide, with the substrate acting as the gate electrode. In a double gate structure, an oxide is used on the upper surface between the source and drain electrodes and an additional metal layer is used on top of this oxide to act as a second gate electrode. Light of broad spectrum or specific wavelength may be used to alter electrical carrier densities in the region between the electrodes to further analyze the electrical properties of the material, or alternatively, the device can be used as a detector of light having a wavelength shorter than the bandgap wavelength of the Si surface.
REFERENCES:
patent: 5663078 (1997-09-01), McCarthy
patent: 5840602 (1998-11-01), Han et al.
patent: 6429145 (2002-08-01), Hovel
patent: 6846715 (2005-01-01), Fitzgerald et al.
“Temperature And Magnetic Field Dependence Of The Carrier Mobility In SOI-Wafers By The Pseudo-MOSFET Method,” Electrochemical Society Proceedings, by C. Rossel, et al., pp. 479-486.
“Si Film Electrical Characterization in SOI Substrates by the HgFET Technique,” Solid State Electronics, by H.J. Hovel pp. 1311-1333, 2003.
“Extremely Low Resistivity Erbium Ohmic Contacts To n-type Silicon,” Physics Letters, by P.L. Janega, et al., pp. 1415-1417.
“The Schottky-barrier Height Of The Contacts Between Some Rare-earth Metals (and silicides) And p-type Silicon,” 1981 American Institute of Physics, by H. Norde, et al., pp. 865-867.
Hovel Harold J.
McKoy Thermon E.
Jr. Carl Whitehead
Pham Thanhha
Trepp, Esq. Robert M.
LandOfFree
Single and double-gate pseudo-FET devices for semiconductor... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Single and double-gate pseudo-FET devices for semiconductor..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Single and double-gate pseudo-FET devices for semiconductor... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3464010