Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
Reexamination Certificate
2006-06-20
2006-06-20
Decady, Albert (Department: 2138)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Memory testing
C714S025000, C706S042000, C700S002000
Reexamination Certificate
active
07065688
ABSTRACT:
In a system having a plurality of processing nodes, wherein each of the plurality of processing nodes has an assigned portion of system memory such that the assigned portion of system memory of each of the plurality of processing nodes is accessible by the plurality of processing nodes, a technique is presented that allows each of the plurality of processing nodes to perform a memory initialization and test of the processing node's assigned portion of system memory. One of the processing nodes can cause the others of the processing nodes to perform the memory initialization and test process or each processing node can automatically perform the memory initialization and test process.
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Mattress Michael V.
Moyes William A.
De'cady Albert
Trimmings John P.
Zagorin O'Brien Graham LLP
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