Simplified process flow for CMOS fabrication

Details Simplified process flow for CMOS fabrication Simplified process flow for CMOS fabrication

1999-09-09

2001-05-22

Bowers, Charles (Department: 2813)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S228000, C438S217000

Reexamination Certificate

active

06235565

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a novel procedure for fabrication of MOSFETs which modifies and eliminates steps required by the prior art to provide a reduced cost and simplified fabrication process.
2. Brief description of the Prior Art
MOSFET fabrication according to a standard prior art process flow requires a large number of steps. It is known that yield generally increases and costs generally decrease by the elimination of and/or alteration of steps in the process flow and such elimination of steps and/or alteration of steps is constantly sought in the art.
Assuming commencement of fabrication with a p-type substrate (it being understood that the procedure can be operated with commencement of fabrication with an n-type substrate with all polarities reversed), an oxide and nitride layer are initially formed in that order and patterned on a substrate surface. An n-type tank is implanted into the substrate through the exposed portion of the pattern and a tank oxide is then formed over the n-type tank by removal of the nitride layer over the n-tank region followed by oxidation of the exposed region. The remaining nitride is removed and, in accordance with the prior art, a relatively low dose p-type tank implant, generally from about 2×10
12
/cm
2
to about 1.3×10
13
/cm
2
at about 50 KeV and preferably about 6×10
12
/cm
2
at 50 KeV is provided in the portion of the surface of the substrate which not masked by the tank oxide to provide a p-type tank. It is well understood that the 50 KeV energy figure used is selected in deference to the type and thickness of masks used or existing and will be sufficiently high to penetrate any mask which is intended to be penetrated and be sufficiently low so as not to penetrate any mask which is not intended to be penetrated. The dopants in the tanks and which will define the tanks are then driven farther into the substrate by annealing to define tank depth. There is then provided a second oxide and nitride deposition with patterning and etching of the second nitride deposition to form the moat or active region for the MOSFET after removal of the tank oxide, the second nitride pattern also permitting growth of a field oxide around the MOSFET, a field oxide over the junction of the n-type tank and the p-type tank. A dummy oxide is then grown over the p-type tank and the n-type tank after removal of remaining nitride. A layer of photoresist is then formed over the n-type tank extending onto the field oxide and leaving the p-type tank exposed. A p-type implant is then provided into the p-type tank to set the threshold voltage of the MOSFET, this being followed by a p-type punchthrough implant in the same region to prevent punchthrough during transistor operation. This is followed by a p-type channel stop implant followed by an implant ashing step to remove the photoresist. The n-type tank region is then patterned in standard manner in both the prior art and in accordance with the present invention to provide a p-channel for a p-channel MOSFET.
SUMMARY OF THE INVENTION
It can be seen that, in accordance with the present invention, the channel profile for the n-channel device is provided by using an optimized p-tank implant dose and an after-tank-drive implant to replace the V
tn
pattern and three V
tn
implants in the prior art MOSFET process. A major difference compared with the prior art is that the process flow in accordance with the present invention utilizes the initially formed tank oxide as a mask for further implantation into the p-type tank as opposed to the removal thereof and replacement with a photoresist as in the prior art. Accordingly, with the tank oxide still in place, there is provided, after the initial p-tank implant, the after-tank-drive implants, these being both a V
tn
implant to set the threshold voltage of the transistor and a channel stop implant for the n-channel transistor. The first high dose implant and drive-in process are used to set the P-tank depth and profile that keeps the transistor out of punchthrough. The second low dose implant is used to set the N-channel threshold voltage and the profile that isolates the transistors in the chip from each other. The significance of the drive in of the first implant prior to the second implant is to keep the channel doping profile and tank profile close to the currently used processes so that the transistor can function in the same manner is with the prior art process flow while simplifying the process flow. If the second implant is used prior to drive-in, a larger dose (>1.9×10
13
/cm
2
) is required to insure proper doping profile in the silicon surface and under the field oxide because the drive-in process makes the dopant species diffuse into the silicon. The larger dose implant before drive-in causes a much deeper P-tank junction and also leads to hot carrier problems. Since an optimized p-tank dose is used, this approach simplifies the prior art NMOSFET process flow while maintaining and even possibly improving the NMOSFET performance. An optimized dose is defined herein as a dose in the range that will not lead to extra channel hot carriers while maintaining the transistor from undergoing punchthrough, these parameters defining the dose range.
More specifically, in accordance with the present invention, the dose of dopant is provided in two steps as opposed to the prior art four step process to provide the same results, the first dose being increased to from about 6×10
12
/cm
2
to about 1.9×10
13
/cm
2
at 50 KeV and preferably about 1.6×10
13
/cm
2
at 50 KeV. The dopants in the tanks are then driven farther into the substrate by annealing. At this point in the fabrication, the process flow in accordance with the present invention again departs from that of the prior art by providing a second low dose p-type implant of from about 1×10
12
/cm
2
to about 8×10
12/cm
2
at 50 KeV and preferably about 3.3×10
12
/cm
2
to set the threshold voltage of the device. The steps performed provide the adjustments required to provide the desired channel profile for an n-channel device. All that remains to complete fabrication is to provide the source/drain regions in standard manner. The p-channel device is fabricated following standard prior art techniques.


REFERENCES:
patent: 5985743 (1999-11-01), Gardner

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