Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
Reexamination Certificate
2007-02-13
2007-02-13
Lamarre, Guy (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital data error correction
C714S801000, C714S794000, C375S265000, C375S341000
Reexamination Certificate
active
10696897
ABSTRACT:
Disclosed is an implementation method for simplifying a complicated message-passing function in a decoder for decoding block codes encoded with low-density parity-check (LDPC) codes and only using a summator and a shifter to simplify the hardware structure of the decoder, in which method the input interval of the message-passing function for binary representation of a message input is divided and the respective divided intervals are linearized to allow the calculation of the output of the message-passing function without using a memory. Based on the fact that the message-passing function is similar in structure to an exponential function, the linearized intervals are set to make the maximum value expressible in each digit of the binary representation as the boundary of the intervals.
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patent: 6938196 (2005-08-01), Richardson et al.
patent: 7013116 (2006-03-01), Ashikhmin et al.
patent: 1020020051549 (2002-06-01), None
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Chang Kyung-Hi
Kim Kwang-Soon
Kim Yun-Hee
Lee Sang-Hyun
Abraham Esaw T.
Blakely & Sokoloff, Taylor & Zafman
Electronics and Telecommunications Research Institute
Lamarre Guy
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