Simplified high speed test system

Details Simplified high speed test system Simplified high speed test system

2005-11-29

2008-08-05

Chung, Phung M (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S701000, C714S703000, C714S738000

Reexamination Certificate

active

07409620

ABSTRACT:
A method for configuring a testing system that includes a step of connecting a commercially available computer (CACMP) for directly controlling transmission of a plurality of test vectors to a test head. The method further includes a step of connecting a test vector memory between the CACMP and the formatter unit (FTM) with response unit (RP) for providing a required data width for storing the test vectors therein.

REFERENCES:
patent: 6671844 (2003-12-01), Krech et al.
patent: 6971045 (2005-11-01), Deb et al.
patent: 7035755 (2006-04-01), Jones et al.
patent: 2004/0078612 (2004-04-01), Kanapathippillai et al.

Affiliated with

Also associated with

Rating

Simplified high speed test system does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Simplified high speed test system, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Simplified high speed test system will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-4005393