Simplified dual damascene process for multi-level metallization

Details Simplified dual damascene process for multi-level metallization Simplified dual damascene process for multi-level metallization

1994-10-11

1997-06-03

Bowers, Jr., Charles L.

Fishing, trapping, and vermin destroying

437190, 437203, 1566521, 1566531, H01L 2144

Patent

active

056354231

ABSTRACT:
A semiconductor device containing an interconnection structure having a reduced interwiring spacing is produced by a modified dual damascene process. In one embodiment, an opening for a via is initially formed in a second insulative layer above a first insulative layer with an etch stop layer therebetween. A larger opening for a trench is then formed in the second insulative layer while simultaneously extending the via opening through the etch stop layer and first insulative layer. The trench and via are then simultaneously filled with conductive material.

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