Simple small feature size bit line formation in DRAM with RTO ox

Details Simple small feature size bit line formation in DRAM with RTO ox Simple small feature size bit line formation in DRAM with RTO ox

1998-11-09

2000-12-19

Bowers, Charles

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438396, 438652, 438657, H01L 218242

Patent

active

061626783

ABSTRACT:
A method for fabricating a type of bit line is able to form a small-sized bit line. In this method a first dielectric layer, a first conductive layer, and a second conductive layer are formed on a substrate in sequence. The first dielectric layer is exposed, then a second conducting wire and a first conducting wire are formed, respectively. A portion of the second conducting wire is removed by a cleaning liquid, so that the feature size of the second conducting wire is less than the feature size of the first conducting wire. An oxide layer is formed on the second conducting wire and the first conducting wire by performing a thermal treatment. The feature size of the second conducting wire is approximately equal to the feature size of the first conducting wire.

REFERENCES:
patent: 5956594 (1999-09-01), Yang et al.
patent: 5981330 (1999-09-01), Jenq
patent: 5981334 (1999-11-01), Chien et al.

Affiliated with

Also associated with

Rating

Simple small feature size bit line formation in DRAM with RTO ox does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Simple small feature size bit line formation in DRAM with RTO ox, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Simple small feature size bit line formation in DRAM with RTO ox will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-270620