Semiconductor device manufacturing: process – Semiconductor substrate dicing – Having specified scribe region structure
Reexamination Certificate
2000-07-05
2003-02-18
Whitehead, Jr., Carl (Department: 2822)
Semiconductor device manufacturing: process
Semiconductor substrate dicing
Having specified scribe region structure
C438S460000, C438S113000, C438S928000, C257S620000
Reexamination Certificate
active
06521513
ABSTRACT:
FIELD OF THE INVENTION
This invention relates in general to a silicon wafer configuration and to a method for forming same. More particularly, the invention relates to a method for singulating a semiconductor wafer comprising a plurality of semiconductor dice arranged along a multiplicity of intersecting streets.
BACKGROUND OF THE INVENTION
Without limiting the scope of the invention, its background is described in connection with semiconductor silicon wafers, as an example.
In semiconductor manufacture, integrated circuits are formed on a wafer formed of silicon or other semiconducting material. In general, layers of various materials, which are semiconducting, conducting or insulating, are utilized to form the integrated circuits. These materials are doped, deposited and etched using various well-known processes. The wafer is also processed resulting in a structure including a large number of individual semiconductor dice or chips.
MicroElectro Mechanical Systems (MEMS) can also be formed on a silicon wafer. Again, layers of various materials, which are semiconducting, conducting or insulating, are utilized to form the MEMS structures. The MEMS structures can also be combined with integrated circuits on the same wafer for control.
Following the device formation process, the wafer is diced to separate the individual dice for packaging or for use in an unpackaged form. The main techniques for wafer dicing are scribing and sawing. With scribing, a diamond tipped scribe is moved across the surface of the wafer along pre-formed scribe lines. These scribe lines are also referred to as “streets.” The diamond scribe forms shallow scratches in the wafer surface. Upon the application of pressure, such as with a roller, the wafer separates along the scribe line. The breaks in the wafer follow the crystal lattice structure of the wafer substrate. Scribing can be used for wafers that are about 10 mils or less in thickness. For thicker wafers, sawing is the preferred method for dicing.
With sawing, a diamond-tipped saw rotating at high rotations per minute (rpms) contacts and saws the wafer along the streets. Sawing can be partially or completely through the wafer. Typically, with saw cutting, the wafer is mounted on a supporting member such as an elastomeric adhesive film stretched across a film frame. When sawing devices, dicing debris from the dicing process is generated on the wafer surface. A protective layer is usually applied to the wafer prior to dicing to protect it from such debris. This protective layer plus any dicing debris attached to it must be cleaned from the devices prior to bonding the device to the package.
One problem with either scribing or sawing is that chips and gouges can form along the severed edges of the die. In addition, cracks can form and propagate from the edges into the substrate of the die. Chipping and cracking are particularly a problem. With scribing, orientation of the chips on the wafer become important because the sides of a rectangular die can be scribed in the <1 1 O> directions only. Consequently, cleaving of a misoriented die results in a jagged separation line. Because of chipping and cracking, additional spacing is required between the dice on the wafer to prevent damage to the microcircuits. As a result, not as many dice can be formed on a standard sized wafer and wafer real estate is wasted.
Another problem in the prior art is that forming irregularly shaped dice or multiple sized dice on the same wafer is difficult or impossible. The formation of multiple sized die on a wafer is advantageous in maximizing the use of silicon “real estate” and reduce waste of material near the periphery of the almost-circular (but for the flat) wafer. However scribing or sawing is most reliably performed in straight lines across the whole wafer. Scribing or sawing in other than straight lines increases the likelihood of producing the previously mentioned chips, ragged edges, gouges and cracks in the silicon wafer. Streets not aligned in the <1 1 O> directions are difficult or impossible to scribe.
MEMS often have structures that are too fragile to survive exposure to some of the standard IC fabrication steps such as device separation and cleanup. An example is the inkjet printhead explained in commonly assigned U.S. patent application Ser. No. 09/017,827 filed on Feb. 3,1998. As described in the aforementioned patent application, the devices contain fluid channels etched through the wafer and oxide membranes with nozzles on the front of the wafer. Dicing such a wafer with conventional sawing methods would damage these thin oxide membranes. Conventionally in sawing, a high-pressure jet of water is used to clear the debris and act as lubricant as well as coolant for the wafer saw. Even though the high-pressure jet of water effectively removes both the debris and excess thermal energy, it represents a source of damage to any structures on the surface of the wafer.
A second example is MEMS that utilize a sacrificial layer, which after removal makes the device extremely fragile. An example is the mechanical grating device explained in commonly assigned U.S. patent application Ser. No. 09/216,289 filed on Dec. 18,1998. As described in the aforementioned patent application, these MEMS have very small beams suspended over an air gap above electrodes formed on the surface of a silicon substrate. Once these structures are formed and the sacrificial material is etched from the air gap, the devices are very fragile. The devices cannot be exposed to liquids, such as would occur during water cleanup steps, without risking destruction of the beams. Therefore, etching of the sacrificial layer and any following steps such as testing are performed after sawing the wafer on individual chips instead of at the wafer level.
However wafer separation prior to device completion results in extensive device handling during the remaining device fabrication steps such as sacrificial material removal and device testing. Performing the remaining steps, especially device testing, on individual devices greatly increases the necessary handling and therefore the cost of the completed devices. Performing these processes in wafer form as opposed to device form greatly reduces the necessary handling because the processing equipment must only move and align to one wafer instead of many devices. Precise alignment is very critical for die testing.
Yet another problem in the prior art is that equipment associated with scribing and sawing is complex and hence costly to install and maintain. Moreover, diamond tipped scribes and saws are expensive and prone to wear out relatively quickly, thereby increasing operating costs.
Consequently, it is desirable to provide means for obviating the need to use diamond-tipped scribes and saws to separate dice formed on silicon semiconductor wafers.
SUMMARY OF THE INVENTION
The present invention provides a method and system for singulating a semiconductor wafer comprising a plurality of semiconductor dice arranged along a multiplicity of intersecting streets having different sizes and/or shapes therein.
The present invention also provides a method and system for singulating a semiconductor wafer that comprises a membrane with circuitry on it and a plurality of dice that can be easily fabricated and severed without destroying the membrane.
It is an object of the invention to provide a method for efficient processing debris intolerant devices allowing sacrificial layer removal and device testing in wafer form.
Accordingly, disclosed in one embodiment is a method for singulating a semiconductor wafer comprising a plurality of semiconductor dice arranged along a multiplicity of intersecting streets. The method comprises lithographically patterning the backside of the semiconductor wafer with a pattern aligned to the streets defined on the front side of the wafer
The method also comprises the step of etching slots through the silicon of the wafer along the streets forming a perforation. The etching step is performed by dry etching methods, and further inclu
Anagnostopoulos Constantine N.
Lebens John A.
Jr. Carl Whitehead
Novacek Christy
Rushefsky Norman
Stevens Walter S.
LandOfFree
Silicon wafer configuration and method for forming same does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Silicon wafer configuration and method for forming same, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Silicon wafer configuration and method for forming same will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3152392