Silicon single crystal, silicon wafer, and epitaxial wafer.

Details Silicon single crystal, silicon wafer, and epitaxial wafer. Silicon single crystal, silicon wafer, and epitaxial wafer.

2002-01-25

2003-11-04

Jones, Deborah (Department: 1775)

Stock material or miscellaneous articles

Circular sheet or circular blank

C428S446000, C423S348000, C117S928000

Reexamination Certificate

active

06641888

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a silicon single crystal used for a semiconductor integrated circuit device and to a silicon wafer and an epitaxial wafer, which are obtained therefrom and used for forming an integrated circuit. More particularly, the present invention relates to a silicon single crystal, a silicon wafer, and an epitaxial wafer exhibiting high gettering capability which is provided by doping with nitrogen solely, or with nitrogen and carbon and/or boron during growth of a single crystal and without provision of an additional step.
DESCRIPTION OF THE PRIOR ART
As the integration density of silicon semiconductor integrated circuit devices rapidly increases, a silicon wafer from which devices are formed is subjected to increasingly severe specifications. Thus, since circuits are made thinner with increasing integration density within a device active region wherein a device is formed on a wafer, crystal defects, such as dislocations and elemental metal impurities other than a dopant, which increase leakage current and shorten the life of a carrier are subjected to more rigorous limitations than ever before.
Conventionally, a wafer produced by slicing a silicon single crystal obtained through the Czochralski method has been used for a semiconductor device. Generally, the wafer contains oxygen at a concentration of about 10
18
atoms/cm
3
. Although oxygen is effective for enhancing the strength of a silicon wafer by preventing generation of dislocations and for providing a gettering effect, oxygen is well known to deposit in the form of an oxide and to induce crystal defects such as dislocation or a stacking fault caused by heating during production of a device. However, in a process of device production, a defect-free DZ layer (denuded zone) having a thickness of about 10 &mgr;m is formed near the wafer surface by diffusion of oxygen to the outside, since the wafer is maintained at a temperature as high as 1100-1200° C. for several hours so as to form a field oxide film through LOCOS (Local Oxidation of Silicon) and a well diffusion layer. The denuded zone serves as a device active region, to thereby provide a reduction in crystal defects.
However, in conjunction with the increasing density of integration, a high-energy ion implantation method has been employed for forming a well, and a device has been produced at a temperature of 1000° C. or less. Therefore, oxygen diffuses slowly, and formation of the above-mentioned denuded zone is insufficient. Even though reduction of oxygen content in a substrate has been attempted, crystal defects are insufficiently suppressed and the performance of a wafer is deteriorated by the reduction in oxygen content. Thus, attempts to reduce oxygen content have yielded unsatisfactory results. Therefore, an epitaxial wafer wherein a silicon epitaxial layer containing substantially no crystal defects has been formed on a silicon slice serving as a wafer substrate has been developed and is widely used for a large-scale integrated device.
Thus, feasibility of complete prevention of crystal defects in a device active region on a wafer can be enhanced by employment of an epitaxial wafer. However, contamination with elemental metal impurities exerts a strong influence, because a complicated process is required for realizing high-density integration and contamination occurs frequently. Although purification of the production environment and raw materials is essential for preventing contamination, complete prevention of contamination in the process of producing the device is difficult. Therefore, gettering is employed. Gettering is a method in which impurity elements provided through contamination are collected outside the device active region so as to eliminate negative influences.
Elemental metal impurities diffuse into a silicon crystal at a relatively low temperature, to thereby form a solid solution, and generally diffuse in silicon at high speed. When crystal defects such as dislocation and distortion caused by fine deposits occur, the impurities tend to concentrate to the defects, in order to attain a more stable energy state than that in the case where impurities exist in the crystal lattice. Therefore, a crystal defect is intentionally introduced to thereby capture and confine impurities. The site where the impurities are captured is called a sink. Sinks are produced by two types of gettering methods; i.e., extrinsic gettering and intrinsic gettering.
Extrinsic gettering is a method in which crystal defects are introduced by means of distortion induced by extrinsic factors such as sandblasting, polishing, laser radiation, ion implantation, and growth of Si
3
N
4
film or polycrystalline Si film; whereas intrinsic gettering is a method in which a number of micro-defects, which are probably induced by oxygen while a wafer obtained through the Czochralski process involving oxygen is alternately subjected to high-temperature heat treatment and low-temperature heat treatment, are employed as sinks.
Of the above-mentioned gettering techniques, extrinsic gettering represented by imparting distortion to a reverse side of a wafer involves drawbacks such as an increase in production costs due to addition of production steps; generation of particles due to detachment of silicon chips from a portion imparted with distortion; and warp of a wafer resulting from the treatment.
In intrinsic gettering, heat treatment is required for effective production of sinks, and therefore intrinsic gettering requires additional steps. Furthermore, in an epitaxial wafer substrate, oxide precipitates which are to serve as nuclei of micro-defects shrink to disappear due to employment of a temperature as high as 1050-1200° C. during a step for forming an epitaxial layer, to thereby disturb subsequent formation of sinks during heat treatment. Particularly, as mentioned above, when a device process is carried out at relatively low temperature, the growth rate of oxide precipitates decreases to disadvantageously result in an insufficient gettering effect to metal impurities at an initial stage of the device process as well as during the entire course of the step.
To overcome these drawbacks, there has been a method employed in which a wafer is thermally treated before and after an epitaxial process in order to intentionally generate crystal defects which getter impurities. Conventionally, a number of gettering methods have been proposed. However, other drawbacks remain, such as a long-duration heat treatment and complex processing steps.
For example, Japanese Patent Application Laid-Open (kokai) No. 3-50186 discloses a method in which a heat treatment is carried out at 750-900° C. before an epitaxial process to thereby ensure generation of oxide precipitates. Although the specific temperature for the heat treatment is not specified, based on assumptions that follow from the description, the heat treatment might be required for as long as four hours or more. Japanese Patent Application Laid-Open (kokai) No. 8-250506 discloses a method in which one-step or two-step annealing at low temperature is carried out; the annealed wafer is maintained within a medium temperature range; and subsequently epitaxial growth is carried out. Furthermore, Japanese Patent Application Laid-Open (kokai) No. 10-229093 discloses a method comprising treating a wafer sliced from a crystal doped with carbon at a concentration of 0.3×10
16
to 2.5×10
16
atoms/cm
3
at 600-900° C. for 15 minutes to four hours; polishing one or both surfaces of the wafer; and carrying out epitaxial growth.
With regard to a heat treatment after an epitaxial process, Japanese Patent Application Laid-Open (kokai) No. 63-198334 discloses a method in which annealing is carried out at 650-900° C. for as long as 4-20 hours, or stepwise temperature elevation between 650° C. and 900° C. is carried out after an epitaxial process to thereby ensure generation of oxide precipitates. Japanese Patent Application Laid-Open (kokai) No. 63-227026 discloses a method in which carbon is doped at a h

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