Silicon oxide based gate dielectric layer

Details Silicon oxide based gate dielectric layer Silicon oxide based gate dielectric layer

2001-02-01

2004-02-17

Fourson, George (Department: 2823)

Semiconductor device manufacturing: process

Coating of substrate containing semiconductor region or of...

Insulative material deposited upon semiconductive substrate

C438S287000

Reexamination Certificate

active

06693051

ABSTRACT:

FIELD OF THE INVENTION The present invention relates to semiconductor devices.
BACKGROUND OF THE INVENTION
In a field effect transistor (“FET”), a capacitance is associated with a gate dielectric layer, which insulates a gate electrode from a channel disposed within a semiconductor substrate. As semiconductor devices continue to be scaled down to reduce power consumption, the demand for higher input FET capacitances has increased. The input capacitance of a FET may be increased by either reducing the thickness of the gate dielectric layer or increasing its dielectric constant.
Gate dielectric layers have historically been realized by bulk silicon dioxide, SiO
2
. To date, industry has been reducing the thickness of bulk silicon dioxide-based gate dielectric layers to increase input FET capacitances. However, at thicknesses of less than about 15 Å, bulk silicon dioxide becomes exceedingly susceptible to leakage currents tunneling through the gate dielectric layer. Thus, the leakage current problem is now becoming a practical concern.
To overcome this leakage current problem, industry has begun to explore various alternatives materials. These alternative materials have a dielectric constant greater than that of bulk silicon dioxide. As input FET capacitance is directly proportional to the dielectric constant of the gate dielectric layer and inversely proportional to the gate dielectric layer's thickness, it is believed that one of these alternative materials may enable the formation of a gate dielectric layer of a sufficient thickness to ameliorate the leakage current problem, while also increasing the input FET capacitance. Typical materials being investigated include metal-silicon-oxynitride and metal silicate, for example.
The use of such alternative materials as gate dielectric layers gives rise to other problems, however. The interface between the alternative materials under consideration and the underlying silicon substrate is of a poorer quality than the interface between bulk silicon dioxide and the silicon substrate. This poorer interface quality, attributable to several factors including an increased number of defects (e.g., dangling bonds) at the silicon interface, as well as the numbers of charges to become trapped by these defects. The trapped charges degrade device performance, reduce the reliability of the gate dielectric layer, and, therefore, reduce the FETs' so-called “mean time between failure.”
SUMMARY OF THE INVENTION
In accordance with our invention, we have recognized that the search for gate dielectric materials other than silicon dioxide is somewhat misplaced. Our invention takes advantage of the silicon dioxide/silicon interface study by two of us, as reported in “The Electronic Structure at the Atomic Scale Of Ultrathin Gate Oxides,” Nature, Vol. 399, June 1999, which theorizes that a layer of silicon oxide (SiO
X<2
) of a sufficient thickness may exhibit a dielectric constant greater than that of bulk silicon dioxide (i.e., about 3.9). In particular, we have now recognized that at least one layer of silicon oxide (SiO
X≦2
), in contrast with bulk silicon dioxide (SiO
2
), may be advantageously employed as a gate dielectric layer. It appears to us now that a layer of silicon oxide at thickness of about 5 Å or less exhibits a dielectric constant greater than about 3.9. More particularly, a layer of silicon oxide apparently exhibits a dielectric constant of about 12 at thickness of about 3 Å. Consequently, it appears that a gate dielectric layer formed from a layer of silicon oxide, SiO
X≦2
, will increase the input FET capacitance, while also providing a desirable interface with a silicon substrate. To further ameliorate leakage current problems—albeit with a somewhat reduced input capacitance—the gate dielectric layer may also comprise a second layer of silicon oxide, SiO
X≦2
, formed upon the first layer of silicon oxide.
We have also recognized that a gate dielectric layer formed from one or two layers of silicon oxide, SiO
X≦2
, each having a thickness of about 5 Å or less, may, however, still be insufficient to withstand damaging leakage current. Consequently, we have also invented a composite gate dielectric layer having a complementary dielectric layer formed upon a layer of silicon oxide, SiO
X≦2
, in accordance with our co-pending, commonly assigned, U.S. Patent application, entitled “A COMPOSITE GATE DIELECTRIC LAYER,” Ser. No. 09/773,442, filed concurrently with the present application. The complementary dielectric layer is of a sufficient thickness to substantially inhibit the flow of leakage current through the gate dielectric layer.
The addition of the complementary dielectric layer will likely reduce the input FET capacitance. As such, the complementary dielectric layer has a dielectric constant greater than that of the layer of silicon oxide. For example, the complementary dielectric layer may be formed from at least one of aluminate, silicate, ZrO
2
, HfO
2
, TiO
2
, Gd
2
O
3
, Y
2
O
3
, Si
3
N
4
, Ta
2
O
5
and Al
2
O
3
. Nonetheless, by judiciously choosing an alternative material for the complementary dielectric layer, and an appropriate thickness, a gate dielectric layer may be provided which exhibits an advantageous combination of properties (i.e., increased capacitance and reduced leakage current, for example) not achieved by the prior art approaches of fabricating a gate dielectric layer.


REFERENCES:
patent: 4783238 (1988-11-01), Roesner
patent: 5937303 (1999-08-01), Gardner et al.
patent: 6074919 (2000-06-01), Gardner et al.
patent: 6251800 (2001-06-01), Sun et al.
patent: 2002/0047151 (2002-04-01), Kim et al.
Klaus et al., “Atomic layer deposition of SiO2 using catalyzed and uncatalyzed self-limiting surface reactions”, Jun.-Aug. 1999, World Scientific, Surface Review and Leeters vol. 6 No. 3-4, pp. 435-448.*
Ymaguchi et al., “Atomic-layer chemical-vapor-deposition of silicon dioxide films with an extremely low hydrogen content”, Jun. 1998, Applied Surface Science vol. 130-132, pp. 202-207.*
Dori et al., “Optimized Silicon-Rich Oxide (SRO) Deposition Process for 5-V-Only Flash EEPROM Applications”, Jun. 1993, IEEE Electron Device Letters, vol. 14, No. 6, pp. 283-285.*
Muller et al., “The electronic structure at the atomic scale of ultrathin gate oxides”, Jun. 24, 1999, Macmillan Magazines LTD, Nature, vol. 399, pp. 758-761.*
“The Electronic Structure At The Atomic Scale Of Ultrathin Gate Oxides”,Nature, vol. 399, Jun. 24, 1999. pp. 758-761.
“Electronic Properties of the Si/SiO2Interface from First Principles”, Physical Review Letters, vol. 85, No. 6, Aug. 7, 2000, pp. 1298-1301.

Affiliated with

Also associated with

Rating

Silicon oxide based gate dielectric layer does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Silicon oxide based gate dielectric layer, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Silicon oxide based gate dielectric layer will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3304619