Silicon-on-insulator (SOI) substrate and method for...

Semiconductor device manufacturing: process – Formation of semiconductive active region on any substrate – On insulating substrate or layer

Reexamination Certificate

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C438S404000, C438S423000, C438S439000, C438S440000, C438S766000

Reexamination Certificate

active

06774016

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a silicon-on-insulator (SOI) substrate and a method for manufacturing the same.
2. Description of the Related Art
As semiconductor devices become highly integrated, current leakage at a junction area undesirably increases the power consumption. Thus, it has become essential for the semiconductor industry to solve this current leakage problem in order to obtain high-speed and low-power semiconductor devices.
More particularly, as the channel length of a transistor decreases to a degree of 0.5 &mgr;m or less, leakage current and the junction capacitance of source and drains of a MOS transistor increase, resulting in an increase of the parasitic capacitance and the power consumption.
In order to overcome such problems, an SOI substrate has been developed to minimize the junction capacitance, the parasitic capacitance and the current leakage.
Various methods for manufacturing the SOI substrate have been known. Generally, two methods are widely used. One of the two methods is called a separation by implanted oxygen (SIMOX) method where oxygen atoms are injected to a predetermined depth of a silicon substrate so that the oxygen atoms penetrate into the predetermined depth of the inner portion of the substrate. Then, the substrate is annealed to manufacture an SOI substrate. In the other method, an insulating layer is formed on wafers. Then, two pre-fabricated wafers with an insulating layer are attached and planarized to form an SOI substrate.
The method of manufacturing an SOI substrate by the conventional SIMOX method and a method of forming an active region by this method will be described in detail with reference to attached
FIGS. 1A-1D
.
FIGS. 1A-1D
are cross-sectional views for explaining a method of manufacturing an SOI substrate and an active region according to the conventional method. The active region is defined by, for example, shallow trench isolation (STI) regions.
Referring to
FIG. 1A
, a wafer is injected with oxygen ions and is heat-treated to form a buried oxide layer
20
, thus forming an SOI substrate including a lower substrate
10
, an oxide layer
20
and an SOI layer
30
.
Referring to
FIG. 1B
, a photoresist is coated on the SOI layer
30
and then is dried to form a photoresist layer. Then, a conventional photo process is performed to form a photoresist pattern
42
in order to expose a surface of the substrate, where a field region is to be formed later.
Referring to
FIG. 1C
, the SOI layer
30
is anisotropically etched, using the photoresist pattern
42
as an etching mask, to form an isolation trench for a field region
34
(FIG.
1
D). Then, the photoresist pattern
42
is removed to expose an SOI layer pattern as an active region
32
.
Referring to
FIG. 1D
, the field regions
34
defining the active region
32
are formed by filling the trench with an insulating material such as Undoped Silicate Glass (USG). Thereafter, a gate insulating layer and a gate electrode are formed on the active region
32
and source and drain regions are subsequently formed by ion implanation.
With the SOI substrate, the source and drain regions of the MOS transistor can be completely separated by field regions. Therefore, a junction capacitance and current leakage can be reduced and high-speed and lower-power-consumption semiconductor devices with improved insulation between the devices can be obtained.
Various methods for manufacturing an SOI substrate using SIMOX are disclosed as follows.
Japanese Patent Laid-Open Publication No. Hei 8-167646 discloses a method of manufacturing an SIMOX substrate having two or more single crystalline silicon thin films having different thicknesses. The SIMOX substrate is manufactured by injecting oxygen ions at a predetermined region of a single crystalline silicon substrate using a silicon oxide mask and subsequent heat-treatment at high temperatures.
Japanese Patent Laid-Open Publication No. Hei 4-67649 discloses a method of forming a device isolation region of an SOI substrate. According to this method, an insulating layer is formed on a semiconductor layer and then is patterned to form an insulating layer pattern. Thereafter, oxygen ions are implanted into the semiconductor layer, using the insulating layer pattern as a mask.
However, according to this method, a local oxidation of silicon (LOCOS) or other isolation trench structures should be formed to accomplish additional device isolation after implementing the oxygen ion injection and heat treatment to form the SOI substrate. Accordingly, the manufacturing process becomes complicated and costly.
On the other hand, according to the second method of manufacturing the SOI substrate, two wafers on which insulating layers are formed are attached using heat treatment and are then etched back. With this method, one wafer is removed through grinding and a high-temperature heat treatment is needed for the attachment of the wafers. Thus, voids might be formed at the contacting portion. In addition, the wafer grinding process is needed and thereby the process becomes complicated and costly.
SUMMARY OF THE INVENTION
The present invention contemplates a novel SOI substrate structure and an improved method for manufacturing the same. The SOI substrate in accordance with one embodiment of the present invention comprises a silicon substrate including an active region defined by a field region. The field region includes a first oxygen-ion-injected isolation region having a first thickness and being formed under the active region. The center of the first region is at a first depth from a top surface of the silicon substrate. The field region of the SOI substrate further includes a second oxygen-ion-injected region having a second thickness greater than the first thickness. The second region is formed at sides of the active region and is also formed from a top surface of the silicon substrate to a predetermined depth. The center of the second ion injected region is at a second depth from the top surface of the silicon substrate. The first and second ion injected regions surround the active region for device isolation. The SOI substrate is formed by performing two sequential ion injecting processes. Because the isolation of the active regions can be achieved by performing the ion injecting process using the sacrificial blocking layer pattern, active regions having various shapes can be obtained simply and less-costly.
According to one embodiment of the present invention, an SOI substrate is manufactured by using an SIMOX method. The same mask can be used for performing two sequential oxygen ion injection processes with different process conditions. A heat treatment is then performed to complete an SOI substrate, in which an active region is separated or surrounded by a field region.
For example, to manufacturing an SOI substrate, a sacrificial blocking layer pattern is formed on a silicon substrate. The sacrificial blocking layer pattern defines and covers an active region. First oxygen ions are introduced at a first energy and at a first dose into a surface of said silicon substrate, using the sacrificial pattern as a mask, to form a first oxygen-ion-injected region in the silicon substrate. Second oxygen ions are introduced at a second energy and a second dose to form a second oxygen-ion-injected region in an upper portion of the silicon substrate uncovered by said sacrificial blocking layer pattern. The second energy and the second dose are less than the first energy and the first dose, respectively. The first and second oxygen-ion-injected regions form a field region that surrounds and isolates the active region.


REFERENCES:
patent: 5918151 (1999-06-01), Tachimori et al.
patent: 5930643 (1999-07-01), Sadana et al.
patent: 6043166 (2000-03-01), Roitman et al.
patent: 6232201 (2001-05-01), Yoshida et al.
patent: 6333532 (2001-12-01), Davari et al.
patent: 6350703 (2002-02-01), Sakaguchi et al.
patent: 6432798 (2002-08-01), Liu et al.
patent: 2309587 (1997-07-01), None
patent: 04-067649 (1992-03-01), No

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