Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2002-04-02
2004-05-18
Smith, Matthew (Department: 2825)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C438S424000, C438S404000, C438S407000, C438S437000, C438S435000
Reexamination Certificate
active
06737706
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly, to a semiconductor device using a silicon-on-insulator (SOI) substrate (hereinafter, referred to as a “SOI device”) and method for manufacturing the same.
2. Description of the Related Art
A SOI substrate, unlike a bulk silicon substrate, has a stacked structure including a base layer, providing a supporting means, a buried oxide layer, and a semiconductor layer, on which devices are formed. SOI devices integrated on such a SOI substrate can be completely isolated from one another by the buried oxide layer. In addition, since the SOI devices can reduce junction capacitance, they provide for reduced power consumption and increased operational speed. As the performance of semiconductor devices continues to improve, the range of applications for SOI devices continues to expand.
Conventional SOI devices will now be described with reference to
FIGS. 1 and 2A
through
2
E. The same reference numerals in different drawings represent the same elements.
FIG. 1
is a cross-sectional view illustrating a conventional SOI device having a trench isolation layer and a method for manufacturing the same. Referring to
FIG. 1
, a substrate
30
comprised of a base layer
10
, a buried oxide layer
15
, and a semiconductor layer
20
is provided. A trench A is formed to define an active region on the semiconductor layer
20
and exposes the buried oxide layer
15
. Next, a thermal oxide layer
32
and a nitride liner
36
are sequentially deposited along the surface of the trench A, and a dielectric layer
37
is formed to completely fill the trench A. Then, an isolation layer
41
, which includes the thermal oxide layer
32
, the nitride liner
36
, and the dielectric layer
37
, is completed. As shown in
FIG. 1
, since the bottom of the isolation layer
41
contacts the buried oxide layer
15
, the isolation layer
41
is referred to as a deep isolation layer.
Next, a gate insulating layer
75
is deposited on the active region, and then a gate electrode
80
is formed. Next, a source/drain region
90
is formed at either side of the gate electrode
80
. The source/drain region
90
, like the isolation layer
41
, is formed such that the bottom of the source/drain region
90
contacts the buried oxide layer
15
. Accordingly, a transistor being formed in the active region can be completely isolated while being surrounded by the isolation layer
41
and the buried oxide layer
15
, and thus junction capacitance can be decreased. Therefore, a SOI device including a deep isolation layer can operate at high speeds.
However, when forming the thermal oxide layer
32
, oxygen atoms may infiltrate into an interfacial portion between the semiconductor layer
20
and the buried oxide layer
15
, and thus an oxidation reaction may occur at the interface between the semiconductor layer
20
and the buried oxide layer
15
. If so, the semiconductor layer
20
may be separated from the buried oxide layer
15
and then may be bent. If the semiconductor layer
20
is bent, a defect, such as dislocation, may occur, and thus leakage current may be caused to increase.
In the SOI device having a deep isolation layer shown in
FIG. 1
, unlike a device using a bulk silicon substrate, a body, i.e., the semiconductor layer
20
, is electrically floated. Thus, when operating the SOI device, electric charge can accumulate under the channel region. The loaded electric charges cause a parasitic bipolar-induced breakdown or latch-up phenomenon and make the operational characteristics of the SOI device unstable. This problem is called a floating body effect.
In order to prevent the floating body effect, an SOI device has been proposed in which an isolation layer is shallowly formed such that the bottom of the isolation layer does not contact the buried oxide layer, a body contact is formed at the semiconductor layer under the isolation layer, and a predetermined voltage is applied to the body contact. The isolation layer may be called a shallow isolation layer, as compared to the deep isolation layer described above. The operational characteristics of the SOI device having the shallow isolation layer are stable; however, the SOI device having the shallow isolation layer has a problem in that junction capacitance increases because a junction portion is generated between the semiconductor layer and the source/drain region.
Recently, various studies have been conducted on a method for manufacturing an isolation layer having a dual trench structure, i.e., a trench having two different depths.
FIGS. 2A through 2E
are cross-sectional views illustrating a conventional SOI device including an isolation layer having a dual trench structure and a method for manufacturing the same. Referring to
FIG. 2A
, a substrate
30
, which includes a base layer
10
, a buried oxide layer
15
, and a semiconductor layer
20
, is provided. A mask pattern
42
, which is comprised of a pad oxide layer
35
and a nitride layer
40
, is formed to expose a region on which an isolation layer for defining an active region on the semiconductor layer
20
will be formed. Next, the semiconductor layer
20
is etched using the mask pattern
42
as an etching mask, thereby forming a shallow trench B in the semiconductor layer
20
. A thermal oxide layer
32
is deposited along the surface of the shallow trench B, and then a photoresist layer pattern
50
is formed on the resulting substrate
30
such that a predetermined portion of the thermal oxide layer
32
on the bottom surface of the shallow trench B is exposed.
Referring to
FIG. 2B
, the thermal oxide layer
32
and the semiconductor layer
20
are etched using the photoresist layer pattern
50
as an etching mask, thereby forming a deep trench C which exposes the buried oxide layer
15
. At the time of etching the thermal oxide layer
32
and the semiconductor layer
20
, the thermal oxide layer
32
formed at a sidewall of the shallow trench B is etched so that the sidewalls of the deep trench C are exposed. Then, a dual trench D comprised of the shallow trench B and the deep trench C and having different depths is completed. Next, the photoresist layer pattern
50
is removed by ashing.
Referring to
FIG. 2C
, a nitride liner
60
is formed on the resulting substrate
30
shown in
FIG. 2B
, and a dielectric layer
65
is formed to completely fill the dual trench D. Next, the resulting substrate
30
is planarized so that the top surface of the nitride layer
40
is exposed. In the case of planarizing the substrate
30
by chemical mechanical polishing (CMP), the top surface of the dielectric layer
65
may become lower than the top surface of the nitride layer
40
due to the difference in the polishing rates between the dielectric layer
65
and the nitride layer
40
.
Referring to
FIG. 2D
, the nitride layer
40
is removed to expose the pad oxide layer
35
. At the time of removing the nitride layer
40
, the nitride liner
60
is partially removed along with the nitride layer
40
so that a groove G is formed between the pad oxide layer
35
and the dielectric layer
65
.
Referring to
FIG. 2E
, the pad oxide layer
35
is removed so that the top surface of the semiconductor layer
20
is exposed. Then, an isolation layer
70
, which includes the thermal oxide layer
32
, the nitride liner
60
, and the dielectric layer
65
in the dual trench D, is completed. Next, a transistor is formed in the active region by a well-known method, thereby completing a SOI device.
As shown in
FIG. 2E
, the bottom of the isolation layer
70
has a step difference.
Since the deep trench C in the isolation layer
70
is formed to contact the buried oxide layer
15
, junction capacitance can be reduced. In the isolation layer
70
, the shallow trench B is formed not to contact the buried oxide layer
15
, and thus the floating body effect can be prevented by forming a body contact at the semiconductor layer
20
and by applying a prede
Kim Byung-sun
Lee Tae-jung
Oh Myoung-hwan
Park Sang-wook
Shin Myung-sun
Luu Chuong A
Mills & Onello LLP
Samsung Electronics Co,. Ltd.
Smith Matthew
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