Silicon-on-insulator chip with multiple crystal orientations

Details Silicon-on-insulator chip with multiple crystal orientations Silicon-on-insulator chip with multiple crystal orientations

2008-05-06

2008-05-06

Lebentritt, Michael (Department: 2812)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

On insulating substrate or layer

C438S151000, C438S152000, C438S155000, C438S198000, C257SE21457

Reexamination Certificate

active

07368334

ABSTRACT:
A silicon-on-insulator chip includes an insulator layer, typically formed over a substrate. A first silicon island with a surface of a first crystal orientation overlies the insulator layer and a second silicon island with a surface of a second crystal orientation also overlies the insulator layer. In one embodiment, the silicon-on-insulator chip also includes a first transistor of a first conduction type formed on the first silicon island, and a second transistor of a second conduction type formed on the second silicon island. For example, the first crystal orientation can be (110) while the first transistor is a p-channel transistor, and the second crystal orientation can be (100) while the second transistor is an n-channel transistor.

REFERENCES:
patent: 3964942 (1976-06-01), Berkenblit et al.
patent: 4072974 (1978-02-01), Ipri
patent: 4753896 (1988-06-01), Matloubian
patent: 4768076 (1988-08-01), Aoki et al.
patent: 4857986 (1989-08-01), Kinugawa
patent: 4908328 (1990-03-01), Hu et al.
patent: 4933298 (1990-06-01), Hasegawa
patent: 5013681 (1991-05-01), Godbey et al.
patent: 5024723 (1991-06-01), Goesele et al.
patent: 5213986 (1993-05-01), Pinker et al.
patent: 5374564 (1994-12-01), Bruel
patent: 5384473 (1995-01-01), Yoshikawa et al.
patent: 5468657 (1995-11-01), Hsu
patent: 5633588 (1997-05-01), Hommei et al.
patent: 5659192 (1997-08-01), Sarma et al.
patent: 5663588 (1997-09-01), Suzuki et al.
patent: 5739574 (1998-04-01), Nakamura
patent: 5759898 (1998-06-01), Ek et al.
patent: 5769991 (1998-06-01), Miyazawa et al.
patent: 5792669 (1998-08-01), Baumann et al.
patent: 5849627 (1998-12-01), Linn et al.
patent: 5863830 (1999-01-01), Bruel et al.
patent: 5882981 (1999-03-01), Rajgopal et al.
patent: 5882987 (1999-03-01), Srikrishnan
patent: 5904539 (1999-05-01), Hause et al.
patent: 6022799 (2000-02-01), Foote et al.
patent: 6023082 (2000-02-01), McKee et al.
patent: 6143070 (2000-11-01), Bliss et al.
patent: 6159824 (2000-12-01), Henley et al.
patent: 6204098 (2001-03-01), Anceau
patent: 6207005 (2001-03-01), Henley et al.
patent: 6252284 (2001-06-01), Muller et al.
patent: 6291321 (2001-09-01), Fitzgerald
patent: 6326285 (2001-12-01), Behfar et al.
patent: 6335231 (2002-01-01), Yamazaki et al.
patent: 6355541 (2002-03-01), Holland et al.
patent: 6358806 (2002-03-01), Puchner
patent: 6368938 (2002-04-01), Usenko
patent: 6407406 (2002-06-01), Tezuka
patent: 6410371 (2002-06-01), Yu et al.
patent: 6410938 (2002-06-01), Xiang
patent: 6414355 (2002-07-01), An et al.
patent: 6429061 (2002-08-01), Rim
patent: 6448114 (2002-09-01), An et al.
patent: 6455398 (2002-09-01), Fonstad, Jr. et al.
patent: 6465316 (2002-10-01), Hattori et al.
patent: 6483171 (2002-11-01), Forbes et al.
patent: 6486008 (2002-11-01), Lee
patent: 6497763 (2002-12-01), Kub et al.
patent: 6531754 (2003-03-01), Nagano et al.
patent: 6534380 (2003-03-01), Yamauchi et al.
patent: 6534382 (2003-03-01), Sakaguchi et al.
patent: 6555891 (2003-04-01), Furukawa et al.
patent: 6562703 (2003-05-01), Maa et al.
patent: 6583440 (2003-06-01), Yasukawa
patent: 6593634 (2003-07-01), Ohmi et al.
patent: 6600170 (2003-07-01), Xiang
patent: 6603156 (2003-08-01), Rim
patent: 6608354 (2003-08-01), Hokazono et al.
patent: 6624488 (2003-09-01), Kim
patent: 6633061 (2003-10-01), Lutzen et al.
patent: 6649492 (2003-11-01), Chu et al.
patent: 6661065 (2003-12-01), Kunikiyo
patent: 6670677 (2003-12-01), Choe et al.
patent: 6690043 (2004-02-01), Usuda et al.
patent: 6815278 (2004-11-01), Ieong et al.
patent: 6835981 (2004-12-01), Yamada et al.
patent: 6861326 (2005-03-01), Gonzalez et al.
patent: 6949420 (2005-09-01), Yamashita
patent: 7141506 (2006-11-01), Endoh et al.
patent: 2001/0001490 (2001-05-01), Sung et al.
patent: 2002/0125475 (2002-09-01), Chu et al.
patent: 2002/0140031 (2002-10-01), Rim
patent: 2002/0185684 (2002-12-01), Campbell et al.
patent: 2003/0013305 (2003-01-01), Sugii et al.
patent: 2003/0080384 (2003-05-01), Takahashi et al.
patent: 2003/0102518 (2003-06-01), Fried et al.
patent: 2003/0104287 (2003-06-01), Yuasa
patent: 2003/0227057 (2003-12-01), Lochtefeld et al.
patent: 2003-229577 (2003-08-01), None
patent: 2003-289144 (2003-10-01), None
Current, M.I., et al., “Atomic-layer Cleaving with SixGeyStrain Layers for Fabrication of Si and Ge-rich SOI Device Layers,” 2001 IEEE SOI Conference, Oct. 1-4, 2001, Durango, CO, Rev. 2, May 10, 2001, pp. 1-3.
Current, M.I., et al., “Atomic-layer Cleavint and Non-contact Thinning and Thickening for Fabrication of Laminated Electronic and Photonic Materials,” 2001 Materials Research Society Spring Meeting, Apr. 16-20, 2001, San Franscisco, CA, Rev 6, Jun. 15, 2001, pp. 1-10.
Current, M.I., “Nanocleaving: An Enabling Technology for Ultra-thin SOI,” Extended Abstracts of International Workshop on Junction Technology 2002, Japan Society of Applied Physics, pp. 97-102.
Langdo, T.A., et al., “Preparation of Novel SiGe-Free Strained Si on Insulator Substrates,” 2002 IEEE International SOI Conference Oct. 2002, pp. 211-212.
Mizuno, T., et al., “Novel SOI p-Channel MOSFETs With Higher Strain in Si Channel Using Double SiGe Heterostructures,” IEEE Transactions on Electron Devices, vol. 49, No. 1, Jan. 2002, pp. 7-14.
Momose, H.S., et al., “Ultrathin Gate Oxide CMOS on (111) Surface-Oriented Si Substrate,” IEEE Transactions on Electron Devices, vol. 49, No. 9, Sep. 2002, pp. 1597-1605.
Rim, K, et al., “Fabrication and Analysis of Deep Submicron Strained-Si N-MOSFET's,” IEEE Transactions on Electron Devices, vol. 47, No. 7, Jul. 2000, pp. 1406-1415.
Stahlbush, R.E., et al., “Annealing of Total Dose Damage: Redistribution of Interface State Density on <100>, <110>, and <111> Orientation Silicon,” IEEE Transactions on Nuclear Science, vol. 35, No. 6, Dec. 1998, pp. 1192-1196.
Wolf, S., et al., “Silicon Processing For The VLSI Era: vol. 1: Process Technology,” Lattice Press, Sunset Beach, CA, pp. cover, 191, 193, and 194.
Satô, T., et al., “Mobility Anisotropy of Electrons in Inversion Layers on Oxidized Silicon Surfaces,” Physical Review B, vol. 4, No. 6, Sep. 15, 1971, pp. 1950-1960.

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