Semiconductor device manufacturing: process – Coating of substrate containing semiconductor region or of... – Multiple layers
Reexamination Certificate
2001-08-31
2002-11-26
Thompson, Craig (Department: 2813)
Semiconductor device manufacturing: process
Coating of substrate containing semiconductor region or of...
Multiple layers
C257S798000
Reexamination Certificate
active
06486077
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATION
This application is based upon and claims priority of Japanese Patent Application No. 2000-266266, filed on Sep. 1, 2000, the contents being incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to formation of a low temperature silicon nitride film, which can be applied for the interlayer insulation film of LSI, for instance.
Since the stray capacitance between two wirings being apart from each other increases if the dielectric constant of the insulating layer is high, it becomes an obstacle in high-speed operation of the device when plural wirings are structured in a multi layer, placing the insulation layer between the wiring layers, stacking one by one, and thereby forming a semiconductor device. Nowadays, it becomes remarkable that the stray capacitance between wirings can be lowered by lowering the dielectric constant of the insulation film material between such layers as much as possible because the insulation film between layers cannot be so thickened along with making of the entire semiconductor device smaller and more integrated, and thereby, trying to obtain higher operating speed performance of the device. At the same time, because recent highly integrated semiconductor devices are desired to be processed in a much lower temperature compared with the conventional process, a lower temperature formation of the interlayer insulating film has been highly demanded recently.
2. Discussion of the Related Art
In accordance with recent developments of higher integration of Large Scale Integration Circuit (LSI), even a semiconductor device element of less than 0.2 &mgr;m minute size is now integrated in the Si substrate surface. LSI can obtain its function by connecting between the semiconductor device elements through wirings. However, if wirings are arranged to make a detour in order to avoid forming unwanted cross-sections with other wirings, then wirings will occupy a large part of the chip surface, and moreover, such long wirings will raise unwanted signal delays. Then, it has been commonly applied that wirings are arranged in a multilayer structure so as to connect with each other up and down through an interlayer insulating film between them.
FIG. 1
illustrates a cross-sectional view of a multilayer wiring structure.
Insulation film
1631
is formed on a silicon substrate
161
, and the contacting plug is formed inside an opening through the insulation film
1631
so that a first wiring
1651
is electrically connected with device formation region
162
. In addition, a second connection is formed between the first wiring
1651
and a second wiring
1652
through a via plug, which is buried in a via hole
1661
opening in an insulation film
1632
, and a third connection is formed between the second wiring
1652
and a third wiring
1653
through a via plug, which is buried in a via hole
1662
opening in an insulation film
1633
. In accordance with the same manner as aforementioned repeatedly in several times, a multilayer wiring structure will be accomplished, and such multilayer formation process will be finalized by covering the uppermost wiring by depositing sealing film
167
.
However, because the multilayer wiring structure is comprised of thin insulation films between wirings, stray capacitance will significantly appear, and it will therefore cause the wiring delay. Also, crosstalk can be caused when each of two high frequency signals flows through each of two wirings isolated by the interlayer insulating film with each other respectively, and thereby misoperation will frequently occur. Such crosstalk problems or signal delays will be prevented if only the interlayer insulating film is formed thick enough to keep a distance between wirings. However, on the other hand, if the interlayer insulating film is thickly formed then it is necessary to deeply open a contact hole or via hole. The formation of a deep contact hole or a deep via hole through such a thick interlayer insulating film should make an opening step more difficult. From the above point of view, the interlayer insulating film should be thinner rather than thicker. For the new generation device later than 256 Mbit DRAM (Dynamic Random Access Memory), a contact hole diameter will be smaller than 0.25 &mgr;m than before along with the development of higher integration. However, for making the opening by dry etching easy, an aspect ratio, namely a ratio between contact hole depth and contact hole diameter, should be no more than 5. If the contact hole diameter should be less than 0.25 &mgr;m and the aspect ratio should be less than 5, then the thickness of the interlayer insulating film is to be as thin as less than 1 &mgr;m.
Meanwhile, as likely as the aforementioned problem between upper and lower wiring layers, the stray capacitance problem might be seriously occurred even between two wirings adjacent to each other disposed on the same interlayer insulating film. This is because, according to miniaturization of the semiconductor device, the distance between wirings as well as the width of such wirings will be shortened. In the near future, inevitably the width of the wiring could be less than 0.25 &mgr;m. It is highly demanded that the wiring intervals should not be expanded because of such miniaturized semiconductor device's super-high integration.
To solve the problem between upper and lower wirings, there is room for doing the effort to thicken the insulation film between interlayer insulating films as much as possible. However, as the function of the circuit is complicated, there becomes no room for designing around, and thus the problem between plural wirings on the same interlayer insulating film will be more serious than the problem between upper and lower wirings.
When the circuit is designed, distribution constant circuit handling is necessary either in the case of the same level wirings or in the case of upper and lower wirings to accurately understand the wiring delay according to the increase of the capacitance between the wirings decided by interlayer insulating film thickness and crosstalk.
FIG. 2
shows the capacitance for each unit wiring length between the wiring layer and the silicon substrate wiring insulated by silicon oxide film of H in thickness (relative dielectric constant 3.9) from which R. L. M. Dang are shown on volume EDL-2 and page 196 of IEEEE Electron Device Letters in 1981. It is shown as the width W of wiring decreases that actual capacitance C greatly increases by a so-called fringe effect compared with the capacitance calculated by the parallel plate electrode approximation. Moreover, when height T of wiring is large at the same time, it is understood that capacitance C increases more and more.
Moreover, according to
FIG. 3
, which is shown in the above reference, total capacitance Cf per unit length between wiring and silicon substrate should be increased along with miniaturization of its wiring intervals only if wiring width W/wiring thickness H exceeds one, because the capacitance C
12
between two wirings isolating so as to have wiring interval S is increased nevertheless capacitance C
11
between wiring and silicon substrate is decreased. That is, each of the device elements could be highly operatable if the device is highly integrated and miniaturized, however, the wiring resistance and stray capacity generally increase if each of inter-element wirings is also highly integrated and miniaturized. As a result, operation speed as the entire LSI will not rise at all.
The result of
FIGS. 2 and 3
is an analytical result concerning the stray capacitance between wiring and the silicon substrate, which are isolated from each other by an interlayer insulating film. Strictly to say, this is not the same result as the stray capacitance between upper and lower wirings. However, circumstances are substantially the same for the stray capacitance between the wiring layers. For instance, Japanese Laid-Open Patent Specification Hei 10-223625 discloses such a problem. Now,
Armstrong Westerman & Hattori, LLP
Fujitsu Limited
Thompson Craig
LandOfFree
Silicon nitride film, semiconductor device, and method for... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Silicon nitride film, semiconductor device, and method for..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Silicon nitride film, semiconductor device, and method for... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2943074