Silicon-germanium devices for CMOS formed by ion...

Active solid-state devices (e.g. – transistors – solid-state diode – Including semiconductor material other than silicon or... – Containing germanium – ge

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C257S192000

Reexamination Certificate

active

06787883

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to methods and apparatus for the manufacture of silicon-germanium semiconductor devices.
BACKGROUND OF THE INVENTION
Complementary metal-oxide-semiconductor (CMOS) technology is widely used in integrated circuits (ICs) due to the lower power consumption of CMOS ICs, as compared to previously preferred NMOS ICs. CMOS is so named because it uses both p- and n-channel transistors in its ICs. However, one of the most fundamental and serious limitations of CMOS technology resides in the p-channel device. Generic, one-micron processes reflect such limitations in the disparate field-effect mobilities associated with n-channel and p-channel devices within a CMOS IC. In such devices, p-channel field-effect hole mobility is approximately two to three times lower than n-channel field-effect electron mobility. Thus, in order to achieve optimum symmetrical switching and driving capabilities, p-channel devices must be more than twice as large as n-channel devices, which undesirably affects packing density of an IC.
To overcome device-operational limitations in bipolar technology, as used in amplifying and switching devices, silicon-germanium (Si
1−x
Ge
x
)/Si heterojunctions were developed. Si
1−x
Ge
x
has an associated band gap that is smaller than that of the silicon. When such a material is used for the emitter material in a bipolar transistor, a higher emitter-injection efficiency is obtained due to the bandgap difference between the silicon base material and the emitter material. To form a Si
1−x
Ge
x
/Si heterojunction, molecular beam epitaxy (MBE) and ultrahigh-vacuum chemical vapor deposition (UHV CVD) are currently used.
It is desirable to adapt Si
1−x
Ge
x
/Si heterojunction technology to improving field-effect mobilities of p-channel MOS devices used in CMOS ICs. However, while MBE and UHV CVD are two methods for forming a Si
1−x
Ge
x
/Si heterojunction, both techniques are not compatible with large-scale manufacturing processes, such as commonly used to form CMOS ICs. MBE and UHV CVD are complicated and expensive. MBE and UHV CVD were developed for use in fabricating bipolar devices, which are intolerable towards microdefects and dislocations resulting from strained layers, due to their extremely small base widths, which require very sharp profiles and transitions. It was not critical to develop an efficient, high volume technique for the fabrication of Si
1−x
Ge
x
layers. Thus, it has not been possible to adapt Si
1−x
Ge
x
/Si heterojunction technology to the large volume manufacture of CMOS ICs. MOS devices are much more tolerant of microdefects and dislocations, since there is no concern about emitter-collector shorts resulting from the extremely small base widths inherent in bipolar devices.
Furthermore, conventional silicon CMOS transistor gates are formed by thermally oxidizing the silicon substrate. When a Si
1−x
Ge
x
layer is formed on a silicon substrate, by MBE or UHV CVD, stable gate oxides can not be later formed on the Si
1−x
Ge
x
layer. Oxides of Ge are not stable, thus, other ways of forming a gate oxide layer are being investigated. One way of forming a stable gate oxide over a Si
1−x
Ge
x
layer is by depositing low temperature CVD oxides. However, such oxides have a resulting undesirable higher surface state density. Another way of forming a stable gate oxide over a Si
1−x
Ge
x
layer is by reoxidation of a silicon cap layer applied over the Si
1−x
Ge
x
layer. However, using a silicon cap layer results in a buried channel structure with an undesirably large effective gate oxide thickness. Furthermore, at high gate voltages, many of the Si
1−x
Ge
x
layer carriers migrate to the silicon cap layer. The net result is a loss in device performance.
There is a need for a method of large volume manufacturing of Si—Ge semiconductor devices. In particular, there is a need for a method of large volume manufacturing of silicon-germanium CMOS ICs, in which a stable gate oxide layer can exist over a Si
1−x
Ge
x
transistor channel.
SUMMARY OF THE INVENTION
The present invention teaches a method and apparatus for large volume manufacturing of Si—Ge complementary metal-oxide-semiconductor (CMOS) integrated circuits (ICs). Si
1−x
Ge
x
is formed under existing gate oxide layers, eliminating the problem of forming stable gate oxides directly over a Si
1−x
Ge
x
layer. A high dose Ge layer is implanted under the gate oxide layer. Next, a Si
1−x
Ge
x
layer is grown by solid phase epitaxial (SPE) regrowth, such that lattice mismatch is minimized between the Si
1−x
Ge
x
layer and the underlying Si substrate. SPE is performed in a low temperature furnace, for approximately ten minutes. Implantation and anneal steps are commonplace in the large volume manufacture of CMOS ICs. Thus, this invention does not add significant cost or complexity to the manufacture of CMOS ICs, while providing the ability to manufacture high volume CMOS ICs with enhanced field effect hole mobility.
According to one aspect of the invention, the Si
1−x
Ge
x
layer formed in this invention has a critical layer thickness, which depends on the molar fraction, x, of germanium present in the Si
1−x
Ge
x
compound formed. As long as the critical layer thickness is not exceeded, Si
1−x
Ge
x
will form defect-free during SPE regrowth. By forming p-channels in accordance with the method of the invention, valuable chip space is conserved, enabling high density chips to be formed. P-channel transistors are able to be formed in approximately the same amount of space as n-channel transistors due to the increased field effect hole mobility, while obtaining symmetrical switching and driving capabilities.


REFERENCES:
patent: 4295897 (1981-10-01), Tubbs et al.
patent: 4394181 (1983-07-01), Nicholas
patent: 5019882 (1991-05-01), Solomon et al.
patent: 5145794 (1992-09-01), Kase et al.
patent: 5254484 (1993-10-01), Hefner et al.
patent: 5272365 (1993-12-01), Nakagawa
patent: 5285088 (1994-02-01), Sato et al.
patent: 5296386 (1994-03-01), Aronowitz et al.
patent: 5298435 (1994-03-01), Aronowitz et al.
patent: 5312766 (1994-05-01), Aronowitz et al.
patent: 5426069 (1995-06-01), Selvakumar et al.
patent: 5461250 (1995-10-01), Burghartz et al.
patent: 5512772 (1996-04-01), Maeda et al.
patent: 5801396 (1998-09-01), Chan et al.
patent: 5818100 (1998-10-01), Grider et al.
patent: 5821577 (1998-10-01), Crabbe′ et al.
patent: 5879996 (1999-03-01), Forbes
patent: 5889292 (1999-03-01), Sameshima et al.
patent: 6118151 (2000-09-01), Tsutsu
patent: 4-34942 (1992-02-01), None
IEEE Electron Device Letters, vol. 12, No. 4, p. 154-156, Apr. 1991 by Nayah et al.*
English language translation of Japanese Kokai 4-34942, Feb. 2000.*
Berti, M., et al., “Composition and Structure of Si-Ge Layers Produced by Ion Implantation and Laser Melting”,J. Mater. Res.,vol. 6, No. 10, pp. 2120-2126, (1991), 10/91.
Berti, M., et al., “Laser Induced Epitaxial Regrowth of Si-xGex/Si Layers Produced by Ge Ion Implantation”,Appl. Surf. Sci. vol. 43,pp. 158-164, (1989), 1/89.
Chilton, B.T., et al., “Solid Phase Epitaxial Regrowth of Strained Sil-xGex/Si Strained-layer Structures Amorphized by Ion Implantation”,Appl. Phys. Lett.,vol. 54, No. 1, pp. 42-44, (1989), 1/89.
Myerson, B.S., et al., “SiGe-Channel Heterojunction p-MOSFET's”,IEEE Trans. on Electron Devices,vol. ED-41, No. 1, pp. 90-100, (Jan. 1994).
Paine, D.C., et al., “The Growth of Strained Si-xGex Alloys on (100) Silicon Using Solid Phase Epitaxy”,J. Mater Re.,vol. 5, No., pp. 1023-1031, (1995),5/90.
People, R., et al., “Calculation of critical layer thickness versus lattice mismatch for GexSil-x/Si strained-layer heterostructures”,Appl. Phys. Lett.,Erratum, 47, 322, (1985), 8/85.
Reedy, R., et al., “High Quality CMOS in Thin (100nm) Silicon on Sapphire”,IEEE Elect. Device Lett,vol. 9, No. 1, pp 32-34, (Jan. 1988).
Wang, K.L., et al., “High Performance GeSi Quantum-Well PMOS on SIMOX”, Proc. Int. Electron Devic

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Silicon-germanium devices for CMOS formed by ion... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Silicon-germanium devices for CMOS formed by ion..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Silicon-germanium devices for CMOS formed by ion... will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-3205620

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.