Silicon barrier layer to prevent resist poisoning

Details Silicon barrier layer to prevent resist poisoning Silicon barrier layer to prevent resist poisoning

1999-10-28

2003-07-01

Utech, Benjamin L. (Department: 1765)

Semiconductor device manufacturing: process

Chemical etching

Vapor phase etching

C438S710000, C438S712000

Reexamination Certificate

active

06586339

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a method of manufacturing a semiconductor device having sub-micron features. The present invention has particular applicability in manufacturing semiconductor devices with a design rule of about 0.15 micron and under having accurately dimensioned gate electrodes with a highly reliable gate dielectric layer thereunder.
BACKGROUND ART
The escalating requirements for high density and performance associated with ultra-large scale integration require responsive changes in various aspects of semiconductor manufacturing techniques. Implementation becomes problematic in manufacturing semiconductor devices having a design rule of about 0.18 micron and under, such as, about 0.15 micron and under, e.g., about 0.12 micron and under.
Semiconductor devices typically comprise a substrate and elements, such as transistors and/or memory cells, thereon. Various interconnection layers are formed on the semiconductor substrate to electrically connect these elements to each other and to external circuits. The formation of interconnection layers and transistor structures is partly accomplished employing conventional photolithographic techniques to form a photoresist mask comprising a pattern and transferring the pattern to an underlying layer or composite by etching the exposed underlying regions.
In accordance with conventional practices, a gate electrode structure is formed by initially forming a thin dielectric layer, such as a silicon oxide layer on a semiconductor substrate, and depositing a conductive layer thereon, such as doped polycrystalline silicon. An anti-reflective coating (ARC) is formed on the conductive layer and a photoresist mask is formed on the ARC. The ARC is typically provided between the photoresist and conductive layers to avoid deleterious reflections from the underlying conductive layer during patterning of the photoresist. ARCs are chosen for their optical properties and compatibility with the underlying conductive layer. However, many ARCs, such as titanium nitride, silicon nitride, and silicon oxynitride, contain basic components, such as nitrogen, which adversely interact with the photoresist material thereon during photolithographic processing, particularly in conventional deep ultra violet (deep-UV) resist processing, e.g., deep-UV radiation having a wavelength of about 100 nm to about 300 nm.
A conventional gate electrode structure is illlustrated in FIG.
1
and comprises substrate
8
and dielectric layer
10
thereon, e.g., silicon dioxide. A conductive layer
12
, e.g., doped polycrystalline silicon, is formed on dielectric layer
10
and ARC
14
, e.g., silicon oxynitride, is formed on conductive layer
12
. A photoresist layer
16
is formed on ARC
14
.
Photoresist coating
16
is typically a deep-UV radiation sensitive photoresist capable of achieving line width resolutions of about 0.15 micron. During photolithographic processing, radiation is passed through mask
18
defining a desired gate electrode pattern to imagewise expose photoresist coating
16
. After exposure to radiation, the photoresist layer is developed to form a relief pattern therein. It has been observed, however, that a residue remains at the photoresist interface and ARC, near the developed photoresist sidewall, resulting in a parabolic appearance
22
a
and
22
b
at the base of the photoresist known as “footing”, as shown in
FIG. 2
, wherein elements similar to those in
FIG. 1
are denoted by similar reference numerals. In
FIG. 2
, reference numeral
20
denotes the photoresist mask. The footing problem is typical of conventional photolithographic techniques employing a photoresist coating over an ARC in forming gate electrode structures, e.g., single or dual gate structures. Footing of the photoresist during patterning, believed to be caused by photoresist poisoning, results in a loss of critical dimensional control in the subsequently patterned gate electrode.
A conventional approach to the footing problem illustrated in
FIG. 2
comprises the formation of a hard mask, such as silicon oxide derived from tetraethyl orthosilicate (TEOS), on the silicon oxynitride ARC to prevent interaction of a basic component, e.g., nitrogen, in the ARC with the deep-UV photoresist mask. However, subsequent to patterning the underlying gate electrode and gate dielectric layer, the hard mask is removed employing a hydrofluoric acid dip prior to removing the ARC by stripping with phosphoric acid. It was found that the hydrofluoric acid dip employed to remove the hard mask, e.g., silicon dioxide, damages the underlying gate dielectric layer, e.g., silicon dioxide layer. As miniaturization proceeds apace and gate dielectric layers become thinner and thinner, the degradation of the gate dielectric layer by hydrofluoric acid attack during removal of the hard mask becomes acutely problematic.
Accordingly, there exists a need for methodology enabling patterning of a gate electrode structure, particularly with deep-UV photoresist techniques, with improved dimensional accuracy and without degradation of the underlying gate dielectric layer.
SUMMARY OF THE INVENTION
An advantage of the present invention is a method of accurately patterning a conductive layer, such as polycrystalline silicon, to form an accurately dimensioned gate electrode structure without degrading the performance characteristics of the underlying gate dielectric layer.
Additional advantages and features of the present invention will be set forth in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from the practice of the present invention. The advantages of the present invention may be realized and obtained as particularly pointed out in the appended claims.
According to the present invention, the foregoing and other advantages are achieved in part by a method of manufacturing a semiconductor device, the method comprising: forming a conductive layer on a dielectric layer; forming an anti-reflective coating (ARC) on the conductive layer; forming an undoped silicon barrier layer on the ARC; forming a photoresist mask on the barrier layer; etching to pattern the conductive layer and dielectric layer forming a gate electrode on a gate dielectric layer; removing the photoresist mask; and etching to remove the barrier layer with high etch selectivity to the gate dielectric layer.
Embodiments of the present invention comprise forming a doped polycrystalline silicon layer on a silicon dioxide layer, forming a silicon oxynitride ARC on the polycrystalline silicon layer, and forming an undoped polycrystalline or amorphous silicon barrier layer, having a thickness of about 10 Å to about 100 Å, on the ARC, forming a photoresist mask on the barrier layer, patterning the gate electrode structure, removing the photoresist mask, stripping the barrier layer with high etch selectivity to the underlying silicon dioxide layer, and removing the ARC.


REFERENCES:
patent: 5773199 (1998-06-01), Linliu et al.
patent: 5792708 (1998-08-01), Zhou et al.
patent: 5856225 (1999-01-01), Lee et al.

Affiliated with

Also associated with

Rating

Silicon barrier layer to prevent resist poisoning does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Silicon barrier layer to prevent resist poisoning, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Silicon barrier layer to prevent resist poisoning will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3089058