Viterbi decoder using a reverse trellis diagram

Details Viterbi decoder using a reverse trellis diagram Viterbi decoder using a reverse trellis diagram

2000-03-29

2003-07-15

Decady, Albert (Department: 2784)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital data error correction

C375S262000, C375S341000

Reexamination Certificate

active

06594795

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a Viterbi decoder for decoding a desired tree code according to a Viterbi algorithm and to a transmitting equipment for coding desired transmission information and then transmitting it to a receiving equipment that incorporates such a Viterbi decoder.
2. Description of the Related Art
Tree codes such as a convolutional code are codes with which the coding gain is kept high in a stable manner without the rate being set high by virtue of the application of a soft decision system according to a Viterbi algorithm to a receiving end even in radio transmission systems in which a high transmission rate and high transmission quality are required in spite of limitations on widening of the transmission bandwidth.
Therefore, in mobile communication systems and satellite communication systems to which such a convolutional code is used, Viterbi decoders are incorporated in many cases in terminals and other equipment that are not only required to be of a low price and a small size but also severely required to be of low power consumption.
FIG. 8
shows the configuration of an exemplary receiving part that incorporates a Viterbi decoder.
As shown in
FIG. 8
, a baseband signal indicating demodulated transmission information is input to a first input of a de-interleaving part
111
. A clock signal (hereinafter referred to as “write clock signal”) that is synchronized with the baseband signal and a clock signal (hereinafter referred to as “read clock signal”) that is locally generated in a non-illustrated receiving part are supplied to second and third inputs of the de-interleaving part
111
, respectively. The output of the de-interleaving part
111
is connected to the input of a branch metric obtaining part
112
. The four outputs of the branch metric obtaining part
112
are connected to the corresponding inputs of an ACS-operation part
113
. The first to fourth outputs of the ACS-operation part
113
are connected to a writing -port of a path memory
114
. Corresponding input/outputs of a maximum likelihood decision part
115
are connected to reading ports of the path memory
114
. Transmission information as a maximum likelihood decision result is obtained at the output of the maximum likelihood decision part
115
.
The de-interleaving part
111
is composed of a dual port RAM
116
whose writing input is given a baseband signal (mentioned above) and whose reading output is directly connected to the input of the branch metric obtaining part
112
, a counter
117
W whose counting output is connected to the write address input of the dual port RAM
116
and whose counting input is given a write clock signal, and a counter
17
R whose counting output is connected to the read address input of the dual port RAM
116
and whose counting input is given a read clock signal.
The branch metric obtaining part
112
is composed of branch metric computing units (BMCU)
120
00
,
120
01
,
120
10
, and
120
11
whose inputs are connected parallel to the outputs of the de-interleaving part
111
(dual port RAM
116
).
The ACS-operation part
113
is composed of adders (
123
001
,
123
012
), (
123
011
,
123
012
), (
123
101
,
123
102
), and (
123
111
,
123
112
) that are disposed at the first stage and one inputs of which are connected to the outputs of the respective branch metric computing units
120
00
,
120
01
,
120
10
, and
120
11
; a comparator (CMP)
124
1
whose first and second inputs are connected to the outputs of the respective adders
123
001
and
123
112
; a comparator (CMP)
124
2
whose first and second inputs are connected to the outputs of the respective adders
123
111
and
123
002
; a comparator (CMP)
124
3
whose first and second inputs are connected to the outputs of the respective adders
123
101
and
123
012
; a comparator (CMP)
124
4
whose first and second inputs are connected to the outputs of the respective adders
123
011
and
123
102
; a selector
125
1
whose first to third inputs are connected to the outputs of the adders
123
001
and
123
112
and the output of the comparator
124
1
and one output of which is connected to a corresponding input of the writing port of the path memory
114
; a selector
125
2
whose first to third inputs are connected to the outputs of the adders
123
111
and
123
002
and the output of the comparator
124
2
and one output of which is connected to a corresponding input of the writing port of the path memory
114
; a selector
125
3
whose first to third inputs are connected to the outputs of the adders
123
101
and
123
012
and the output of the comparator
124
3
and one output of which is connected to a corresponding input of the writing port of the path memory
114
; a selector
125
4
whose first to third inputs are connected to the outputs of the adders
123
011
and
123
102
and the output of the comparator
124
4
and one output of which is connected to a corresponding input of the writing port of the path memory
114
; a flip-flop (FF)
126
1
that is disposed between the other output of the selector
125
1
and the other inputs of the adders
123
001
and
123
111
; a flip-flop (FF)
126
2
that is disposed between the other output of the selector
125
2
and the other inputs of the adders
123
101
and
123
011
; a flip-flop (FF)
126
3
that is disposed between the other output of the selector
125
3
and the other inputs of the adders
123
112
and
123
002
; and a flip-flop (FF)
126
4
that is disposed between the other output of the selector
125
4
and the other inputs of the adders
123
012
and
123
102
.
The maximum likelihood decision part
115
is composed of a counter
131
whose output is connected to the address input of the first reading port of the path memory
114
, a shift register
128
whose output is connected to the address input of the second reading port of the path memory
114
and whose input is connected to the reading output of the path memory
114
, a trace memory
129
whose input is connected to the output of the path memory
114
and that is disposed at the final stage, and an address controller
130
whose output is connected to the address input of the trace memory
129
.
In the conventional example having the above configuration, a baseband signal is generated by a demodulator (not shown) for demodulating a received wave that has been received from a transmitting end through a radio transmission channel, the baseband signal being given as an array of code blocks that have been subjected, on the transmitting end, to “interleave processing” (see FIG.
9
(
a
)) for distribution on the time axis to prevent deterioration in transmission quality due to burst errors that may occur on the radio transmission channel.
In the de-interleaving part
111
, the counter
117
W generates write addresses by counting cyclically write clocks that are synchronized with the baseband signal. The counter
117
R generates read addresses by counting read clocks (mentioned above) cyclically.
An array of code blocks (mentioned above) that are given as a baseband signal are sequentially written to storage areas of the dual port RAM
116
in a write address updating order (i.e., in the row direction) indicated by symbol (1) in FIG.
9
(
b
).
The code blocks that have been written in the storage areas of the dual port RAM
116
in the above manner are sequentially read out in a read address updating order (i.e., in the column direction) indicated by symbol (2) in FIG.
9
(
b
).
A bit string representing an array of code words read out from the dual port RAM
116
will be referred to simply as “received sequence” and received signals at time point t is denoted by (I
t
Q
t
). Although received signals (I
t
Q
t
) may be represented by multiple values with soft decision, for the sake of simplicity it is assumed here that each of I
t
and Q
t
is represented by a binary value, that is, “0” or “1”.
In the branch metric obtaining part
112
, the branch metric computing units
120
00
,
120
01
,
120
10
, and
120
11
compute,

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