Silicon and arsenic double implanted pre-amorphization process f

Details Silicon and arsenic double implanted pre-amorphization process f Silicon and arsenic double implanted pre-amorphization process f

1998-08-07

2000-03-14

Booth, Richard

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438305, 438592, 438528, H01L 218238, H01L 21336

Patent

active

060372044

ABSTRACT:
A method for forming salicide contacts and polycide conductive lines in integrated circuits is described which employs the ion implantation of both silicon and arsenic into polysilicon structures and into source/drain MOSFET elements is described. The method is effective in reducing gate-to-source/drain bridging in the manufacture of sub-micron CMOS integrated circuits and improving the conductivity of sub-micron wide polycide lines. Silicon is implanted into the polysilicon and into the source/drain surfaces forming a amorphized surface layer. Next a low dose, low energy arsenic implant is administered into the amorphized layer. The low dose shallow arsenic implant in concert with the amorphized layer initiates an equalized formation of titanium silicide over both NMOS and PMOS devices in CMOS integrated circuits without degradation of the PMOS devices. Amorphization by the electrically neutral silicon ions permits the use of a lower dose of arsenic than would be required if arsenic alone were implanted. In addition to amorphization, the implanted silicon prevents the formation of microvoids by providing silicon towards titanium silicide formation. The combined amorphization effect of the silicon and arsenic implants also facilitates a silicide phase transition on sub-micron wide polycide lines thereby improving their conductivity.

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