Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Patent
1996-11-12
1999-12-07
Booth, Richard
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
438535, H01L 21336
Patent
active
059982721
ABSTRACT:
A process in accordance with the invention minimizes the number of heat steps to which an source-drain extension region is exposed, thus minimizing source-drain extension region diffusion and allowing more precise control of source-drain extension region thickness over conventional processes. In accordance with the invention, spacers are formed abutting the gate and then heavily doped source and drain regions are formed. The gate and source and drain regions are silicided. The spacers are subsequently removed and source-drain extension regions are then formed. In one embodiment of the invention, a laser doping process is used to form the source-drain extension regions.
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A Shallow Junction Submicrometer PMOS Process Without High-Temperature Anneals; P.G. Carey, K.H. Weiner and Thomas W. Sigmon; IEEE Electron Device Letters, vol. 9, No. 10, Oct. 1988.
Raised Source/Drain MOSFET with Dual Sidewall Spacers, M. Rodder and D. Yeakley, IEEE vol. 12, No. 3 (Mar. 1991).
Fabrication of sub-40-nm p-n junctions for 0.18 .mu.m MOS device applications, Weiner & McCarthy, SPIE V.2091 (Sep. 1993).
New Methods of Shallow Junction Formation in Silicon Using Gas Immersion Laser Doping, Ishida, SSEL (Sep. 1994).
Ishida Emi
Ju Dong-Hyuk
Luning Scott
Advanced Micro Devices , Inc.
Booth Richard
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