Signal testing of integrated circuit chips

Details Signal testing of integrated circuit chips Signal testing of integrated circuit chips

2007-10-23

2007-10-23

Britt, Cynthia (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S745000

Reexamination Certificate

active

10614040

ABSTRACT:
A method for testing signals of integrated circuits (ICs). According to the invention, a first IC chip successively drives a number of test patterns one at a time. At the receiving end, a second IC chip latches in the test patterns one by one. Meanwhile, the second IC chip determines whether a currently latched test pattern is correct or not. If it is incorrect and at least an error bit occurs, depending on the type of the test patterns, the second IC chip indicates that there exists ground bounce or power bounce in a signal trace corresponding to the error bit.

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“Validation And Test Issues Related to Noise Induced by Parasitic Inductances of VLSI Interconnects” by Sinha et al. IEEE Transactions on Advanced Packaging Publication Date: Aug. 2002 vol. 25 Issue: 3 pp. 329-339, INSPEC Accession No. 7496558.

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