Signal receiver in an interface

Details Signal receiver in an interface Signal receiver in an interface

1995-09-26

1997-06-17

Hudspeth, David R.

Electronic digital logic circuitry

Signal sensitivity or transmission integrity

Signal level or switching threshold stabilization

326 24, 327206, H03K 1730

Patent

active

056401043

ABSTRACT:
A signal receiver for an interface of an MPU or a memory has a differential amplifier for receiving an input signal from an input/output line for the IPU and the memory, an inverter for receiving the output of the differential amplifier, and a feed-back section for providing the signal receiver with a transfer characteristic having a hysteresis with respect to the input signal of tile signal receiver. The feed-back section includes a feed-back signal path and a feed-back current path formed between a supply line and the output of the differential amplifier. The output signal of the gate is feed-backed to the feed-back current path as a control signal for making the feed-back current path active or inactive to shift tile voltage level of the output of the differential amplifier. The gate is not operated by a transient oscillation of the input signal so that unnecessary power consumption due to tile transient oscillation of the input of tile signal receiver is avoided.

REFERENCES:
patent: 4926068 (1990-05-01), Fujita
patent: 5107137 (1992-04-01), Kinugasa
patent: 5362994 (1994-11-01), Lin
patent: 5444413 (1995-08-01), Kimura
patent: 5459437 (1995-10-01), Campbell
patent: 5463339 (1995-10-01), Riggio

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