Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
1999-08-03
2002-02-19
Moise, Emmanuel L. (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S030000
Reexamination Certificate
active
06349397
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a signal processing apparatus having at least a central processing unit (CPU) and a non-volatile memory capable of being rewritten from the outside and a programming method of the non-volatile memory.
2. Description of the Related Art
In recent years, along with the improvement of the technology for production of semiconductors, semiconductor devices with high integration and high density are becoming easier to realize. For example, a large number of semiconductor devices have been realized by integration of CPUs and memories and other different types and applications of semiconductor circuits on a single substrate such as with application-specific integrated circuits (ASIC).
As an example of such a semiconductor device, there is for example a semiconductor device with a CPU and a non-volatile memory for storing a program for controlling the operation of the CPU and further a memory to and from which ordinary data is written and read, for example, an SRAM, formed together on its substrate. In this, as the non-volatile memory for storing the program, for example, there are a read-only memory (ROM) or an EEPROM or flash EEPROM which are capable of rewriting and storing written data semipermanently.
In such a semiconductor device, by rewriting the program stored in the non-volatile memory in accordance with need from the outside, a programmable semiconductor device can be realized, different functions can be realized in response to the requests of users, and a semiconductor device of a high flexibility can be provided.
In such programmable semiconductor devices, there are different types of rewritable non-volatile memories. The rewriting routines differ depending on the type. In the past, the rewriting had been carried out according to the rewriting routines inherent to the semiconductor devices. Here, the program for performing the rewriting routine is called a data rewriting program. That is, generally, it is necessary to prepare a rewriting program for each semiconductor device using a different type of non-volatile memory.
In order to rewrite the programming codes, data, and so forth stored in the non-volatile memory of a semiconductor device (hereinafter simply referred to as “data” for convenience), usually a writing device is connected to the semiconductor device to be rewritten and that writing device is used to rewrite the data while as controlling the operation of the CPU in the semiconductor device. Note that the data rewriting being referred to here includes, for example, erasure of data, partial erasure, verification after writing, and so forth according to need depending on the type of the non-volatile memory.
As one example of a rewriting device of a non-volatile memory in a semiconductor device, there is the art disclosed in Japanese Unexamined Patent Publication (Kokai) No. 5-189584. In this example, a data rewriting program is loaded in advance into the semiconductor device. Namely, a memory, for example, a ROM, for storing the data rewriting program is provided in the semiconductor device. When rewriting the data, a CPU loads the data rewriting program from the ROM, then controls the data rewriting in accordance with the loaded program.
FIG. 1
shows an example of the configuration of a system constituted by a semiconductor device and a writing device for rewriting data to the semiconductor device. As illustrated, the semiconductor device
10
a
is constituted by a microprocessor
20
a,
a switch
30
, functional circuits
40
,
50
, and a connector
70
. The writing device
60
transfers writing data to the microprocessor
20
a
through the connector
70
to provide rewriting data and commands necessary for data rewriting to the microprocessor
20
a.
The microprocessor
20
a
is constituted by a ROM switching circuit
21
, a flash EEPROM
22
, a data receiver (UART)
23
, a CPU
24
, a ROM (Boot ROM)
25
, and an SRAM
26
.
Each component circuit in the microprocessor
20
a
mentioned above transfers data and control signals through a data bus and control signal line (hereinafter simply referred to as a “bus” for convenience). Furthermore, the microprocessor
20
a
transfers data or control signals with the functional circuits
40
and
50
through the same bus
100
.
In the microprocessor
20
a,
the data receiver
23
receives data from the writing device
60
and transfers it to the CPU
24
through the bus
100
.
The CPU
24
outputs the data or control signals to the other component circuits through the bus
100
to control the operations of the component circuits.
The ROM switching circuit
21
outputs an enable signal for enabling the flash EEPROM (hereinafter referred to as flash memory)
22
or the ROM
25
in accordance with a switching signal S
30
from the switch
30
.
The flash memory
22
stores commands or other data for controlling the operation of the CPU
24
. Note that the stored data in the flash memory
22
is rewritten based on the control of the writing device
60
.
The ROM
25
stores the data rewriting program.
The SRAM
26
temporarily holds the data transferred through the bus
100
and outputs the held data to the other component circuits.
During ordinary operation, a signal S
30
having a certain fixed level is output from the switch
30
. The ROM switching circuit
21
outputs the enable signal to the flash memory
22
accordingly. In this case, during the initialization of the semiconductor device
10
a,
the CPU
24
loads commands and data from the flash memory
22
selected by the ROM switching circuit
21
, then operates in accordance with the loaded commands. For example, the CPU
24
controls the operations of the functional circuits
40
and
50
through the bus
100
to realize a desired function.
The data is rewritten by the routine shown in the flow chart of FIG.
2
. In data rewriting, a control signal S
c
for switching the switch
30
is input from the writing device
60
. Accordingly, the switch
30
switches (step SS
1
) and outputs a signal S
30
different from that of the ordinary operation.
The ROM switching circuit
21
outputs the enable signal to the ROM
25
according to the signal S
30
from the switch
30
. Consequently, after the initialization of the semiconductor device
10
a
(step SS
2
), the data rewriting program is loaded from the ROM
25
selected by the ROM switching circuit
21
(step SS
3
) and the rewriting is controlled in accordance with the loaded commands. For example, the CPU
24
communicates with the writing device
60
through the data receiver
23
(step SS
4
), erases the flash memory
22
(step SS
5
), then once stores the rewriting data input from the writing device
60
into the SRAM
26
(step SS
7
), then writes the rewriting data stored in the SRAM
26
to the flash memory
22
(step SS
8
). Then, the CPU
24
judges whether the writing is finished or not (step SS
9
) and, if it is not finished, returns to step SS
6
, where it receives the next writing data from the writing device
60
and writes it into the flash memory
22
.
When the data rewriting of the flash memory
22
is carried out normally, the CPU
24
switches the switch
30
, and the ROM switching circuit
21
selects the flash memory
22
(step SS
10
). Accordingly, after the initialization of the semiconductor device
10
a
(step SS
11
), the rewritten program and data are loaded to the CPU
24
from the flash memory
22
, and the system starts (step SS
12
).
In the flow chart of
FIG. 2
, in the operations from steps SS
3
to SS
9
, the CPU
24
is controlled by the rewriting program loaded from the ROM
25
. During this period, the program or data in the flash memory
22
is rewritten by the new program or data input from the writing device
60
. In the other operation steps, the CPU
24
is controlled by the program loaded from the flash memory
22
. Especially, in steps SS
10
to SS
12
after the data rewriting, the CPU
24
is controlled by the rewritten program in flash memory
22
.
However, in the above-mentioned conven
Arai Hiroaki
Koga Kiyokazu
Kananen, Esq. Ronald P.
Moise Emmanuel L.
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