Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
Reexamination Certificate
1999-06-01
2002-12-10
Decady, Albert (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital data error correction
C341S059000, C341S094000, C375S341000
Reexamination Certificate
active
06493846
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a signal processing apparatus and method capable of suppressing the generation of burst error, and to a data recording/reproducing apparatus using the same.
2. Description of Related Art
The magnetic disk recorder represented as a data recording/reproducing apparatus has been more and more requested to have a capability of higher recording density, and the signal processing technology in the recording/reproducing system for supporting this request has also been developed toward the higher recording density capability.
In order to cope with the S/N ratio reduced by the intersymbol interference associated with high density recording, a partial response equalization system has been employed. For example, PRML (Partial Response with Maximum Likelihood detection) class 4 has been used to detect a signal sequence nearest to a reproduced signal by means of a known interference caused in a reproducing channel, and it is already utilized in the magnetic disk recorder.
FIG. 1
shows a flow of digital information reading processing in the conventional EEPRML (Extended Extended PRML). A signal
1
read from a head is equalized by a PR equalizer
2
into a signal
3
. Then a decoded data sequence
5
that was actually recorded is estimated from the signal
3
by a maximum likelihood decoder
4
. The estimated coded sequence
5
is supplied through a postcoder
6
to a 16/17 code demodulator
10
, where it is decoded into an information data sequence
11
. The information data sequence
11
undergoes error detection and correction in a Reed-Solomon decoder
12
.
The most of the error sequences in the maximum likelihood decoder
4
have a short distance from a correct sequence. The error sequences with shorter distances from the correct sequence are examined by use of an error flow graph.
FIG. 2
is a schematic graph of error flow within a distance of 8 from the correct sequence in EEPRML. In each state (e
t-3
e
t-2
e
t-1
e
t
), e
t
represents error at time t. When e
t
is 0, the corresponding bit has no error. Similarly when e
t
is respectively + and −, the corresponding bits “0” and “1” have errors of “1” and “0”, respectively. The numbers attached on the arrows in the flow diagram indicate the distance from the correct sequence that increase with the transition of the corresponding errors. From
FIG. 2
, it will be understood that the error sequences from the maximum likelihood decoder
4
in EEPRML have errors of ±(+−+) (three consecutive errors), ±(+−+− . . . ) (four or more consecutive errors), and ±(+−+00+−+) in the order of shorter distance from the correct sequence. The frequency of actual error occurrence is affected not only by the distance from the correct sequence but by the mutual correlation between the error length and noise. The actual error is likely to occur in order of errors of three consecutive bits, one bit, two bits, five bits and four bits. Where, the error of four consecutive bits “0101 . . . ” is represented as “1010 . . . ” or vice versa.
Also by use of more advanced PRML or by slightly moving coefficients of partial response the frequency order is somewhat changed, but error tendency is not changed.
The short errors on the modulated codes in the maximum likelihood decoder
4
are expanded into burst error by the demodulator
10
. If, for example, 16/17 modulation code is used, the worst expansion is 4 bytes. This corresponds to the worst value in the case where errors occur at the final bit of 16/17 code and are propagated to the next code word by the postcoder
6
. This error expansion causes the correction ability of Reed-Solomon code to be reduced.
SUMMARY OF THE INVENTION
Accordingly, it is an object of the invention to realize a signal processing apparatus and method capable of reducing burst error to a small value, and provide a highly reliable data recording/reproducing apparatus using the same.
In order to achieve the above object, a signal processing apparatus according to the invention has a simple error detection/correction circuit provided just before the modulated code demodulator. The simple error detection/correction circuit can be an error detection/correction circuit using a linear error correction code, for example, an error detection/correction circuit using an error correction code (CRCC) constructed by a cyclic code.
Moreover, data reproducing means of a data recording/reproducing apparatus is constructed by using this signal processing apparatus.
Since some error patterns, that are easy to occur in the maximum likelihood decoder, can be corrected before the modulated code demodulator by constructing the signal processing apparatus as mentioned above, the burst error after the demodulator can be reduced.
REFERENCES:
patent: 5134635 (1992-07-01), Hong et al.
patent: 5442646 (1995-08-01), Chadwick et al.
patent: 5675565 (1997-10-01), Taguchi et al.
patent: 5809060 (1998-09-01), Cafarella et al.
patent: 6029264 (2000-02-01), Kobayashi et al.
patent: 6148431 (2000-11-01), Lee et al.
NN9403175 (Method For DC Suppression without Violating the Run-Length Constraints; IBM Technical Disclosure Bulletin, Mar. 1994, US; vol. No.: 37, Issue No.: 3, Page No.: 175-178).
Kondo Masaharu
Mita Seiichi
De'cady Albert
Hitachi , Ltd.
Lamarre Guy
Mattingly Stanger & Malur, P.C.
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