SiGe nickel barrier structure employed in a CMOS device to...

Details SiGe nickel barrier structure employed in a CMOS device to... SiGe nickel barrier structure employed in a CMOS device to...

2006-07-18

2006-07-18

Tsai, H. Jey (Department: 2812)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S300000, C438S303000, C438S653000

Reexamination Certificate

active

07078285

ABSTRACT:
A CMOS device such as an NFET or a PFET and a method of forming a CMOS device are provided. The method begins by forming at least one patterned gate region atop a first semiconductor layer that includes silicon. Dielectric spacers are formed about exposed portions of the patterned gate region. Source-drain regions are formed in the first semiconductor layer. Recesses are formed in the first semiconductor layer that extends under the dielectric spacers. The first semiconductor layer has exposed surfaces that in part define sidewalls of the recesses. A nickel barrier layer is formed on each of the exposed surfaces of the first semiconductor layer. The nickel barrier layers are etched so that the nickel barriers remain only on portions of the exposed surfaces located under the dielectric spacers and not on remaining portions of the exposed surface. A silicon-containing layer is formed on the remaining exposed surfaces of the first semiconductor layer. Silicide layers are formed on the silicon-containing layers, wherein the silicide layer includes nickel.

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