Sidewalls for guiding the via etch

Details Sidewalls for guiding the via etch Sidewalls for guiding the via etch

1999-09-22

2001-06-12

Whitehead, Jr., Carl (Department: 2822)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified configuration

C257S758000

Reexamination Certificate

active

06246120

ABSTRACT:

BACKGROUND AND SUMMARY OF THE INVENTION
The present invention relates to interconnect structures and fabrication methods.
Background: Via Alignment
As device dimensions shrink, the margin between the edges of vias and the edges of interconnects decreases. If a via is patterned such that it does not completely overlie an interconnect, the material along the side of the interconnect may undesirably be removed during the via etch, resulting in an increase in contact resistance. Also, there may be materials between the interconnects, which if exposed during via etch, can cause problems during the filling of the vias, such as via poisoning. The occurrence of via misalignment increases in “zero-overlap” via/interconnect designs, in which the area of the interconnect equals the area of the via.
One conventional approach selects the dielectric material such that the via etch preferentially etches the portion of the dielectric which is on top of the interconnects. In addition, a liner layer is typically used over the interconnects to serve as a buffer layer to subsequently deposited dielectrics by gettering impurities from the sides of the interconnects. However, the buffer layer is usually a dielectric material, such as silicon oxide or PETEOS, which may not be conformally deposited.
Another conventional technique for ensuring that a reliable contact will still be made in the event of an error in contact via placement is to form a thick buffer region
320
, which can be composed of a dielectric, conductive nitride, polysilicon, or metal, on the sidewalls of the interconnect
310
to serve as an etch stop in order to protect the underlying layer
300
, as shown in prior art FIG.
3
. This conventional technique is discussed in U.S. Pat. No. 5,321,211 to Haslam et al., which is hereby incorporated by reference. However, with this structure, the via hole must fall entirely on top of the interconnect/buffer area in order to protect the underlying layers.
Sidewall Structures and Methods
The present application discloses structures and methods for guiding the via etch by depositing a thin sidewall layer, preferably titanium nitride (TiN), on the interconnects. Parallel extensions of this thin side layer of TiN above the surface of the interconnect can direct the via etch to the top of the interconnect, and thus prevent etching down the side of the interconnect and exposure of materials residing between the interconnects. Unlike the Haslam et al. patent, which requires the via etch to fall entirely on the interconnect/buffer area, the present inventors have discovered that the use of parallel extensions of a thin sidewall layer allows the via etch to miss the interconnect/sidewall area by up to twenty-five percent of the via diameter.
Advantages of the disclosed methods and structures include:
simple and effective method to etch aluminum interconnects;
increases back-end-of-line yield by saving misaligned vias;
lowers the resistance and improves the reliability of “zero-overlap” vias;
thickness of the sidewall material can be minimized because of the conformal nature of the deposition; and
a wider range of dielectric materials can be integrated into structures, without the need for a PETEOS liner layer.


REFERENCES:
patent: 5321211 (1994-06-01), Haslam et al.
patent: 5462893 (1995-10-01), Matsuoka et al.
patent: 5619072 (1997-04-01), Mehta
patent: 5641708 (1997-06-01), Sardella et al.
patent: 5702981 (1997-12-01), Maniar et al.
patent: 5756396 (1998-05-01), Lee et al.
patent: 5808364 (1998-09-01), Cronin et al.
patent: 5827437 (1998-10-01), Yang
patent: 5852328 (1998-12-01), Nishimura et al.
patent: 5969425 (1999-10-01), Chen et al.
patent: 6023083 (2000-02-01), Tomita
patent: 6037630 (2000-03-01), Igarashi et al.

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