Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified material other than unalloyed aluminum
Reexamination Certificate
1996-01-11
2001-10-16
Clark, Sheila V. (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Of specified material other than unalloyed aluminum
C257S771000
Reexamination Certificate
active
06303995
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to metal interconnects in integrated circuit structures. More particularly, this invention relates to the formation of retention sidewall structures on the sides of metal interconnects to prevent lateral deformation of the metal interconnect.
2. Description of the Related Art
In the formation of integrated circuit structures, one or more patterned metal layers or “interconnects” are formed between insulation layers, e.g., between silicon oxide layers. Typically, each of such patterned metal layers actually comprises a sandwich of several electrically conductive layers including a main metal layer which usually comprises an aluminum layer or a layer of an aluminum alloy, such as an aluminum/copper (Al—Cu) alloy or an aluminum/copper/silicon (Al—Cu—Si) alloy. This main layer, which is principally selected for its conductivity, is typically sandwiched in between a thin lower layer of titanium and thin upper layers of titanium and titanium nitride. These thin layers are relatively hard, compared to the main layer, and serve to prevent vertical deformation of the aluminum-containing main layer during subsequent processing, especially during thermal processing such as annealing. Thus, for example, the formation of hillocks or volcanos by upward expansion of the main aluminum-containing layer is inhibited.
However, the patterning of such metal and other electrically conductive layers to form the desired metal interconnects or “wiring harness” extends through all of the electrically conductive layers, thereby exposing the sidewalls of the main metal layer. Subsequent exposure to heat, for example, by annealing of the structure can result in undesirable lateral deformation and expansion of the main metal layer.
FIG. 1
shows a typical prior art construction of a patterned multilayer construction just after the patterning step and prior to exposure of the patterned structure to further processing, particularly heat generating processing such as any subsequent annealing. In
FIG. 1
, an integrated circuit structure
2
comprising a semiconductor wafer, is shown having a first insulation layer
4
formed thereon, such as a silicon oxide layer, and two metal lines
10
and
12
formed over insulation layer
4
. Each metal line comprises the patterned portions of: a first titanium layer
16
formed over oxide layer
4
; a first titanium nitride layer
18
formed over titanium layer
16
; a main metallic layer
20
, comprising an aluminum-containing alloy, formed over first titanium nitride layer
18
; and a second titanium nitride layer
26
formed over aluminum-containing layer
20
. A second oxide layer
30
is shown formed over and between metal lines
10
and
12
.
FIG. 2
shows the same structure as
FIG. 1
, but after subsequent processing of the structure, including exposure to elevated temperature, such as, for example, an annealing step carried out at about 600° C. It will be noted that main aluminum-containing layer
20
has deformed, at least in part due to the stresses formed therein from exposure to heat, causing lateral expansion of main metal layer
20
in each metal line, at
22
. Depending upon the spacing between adjacent metal lines, such expansion could eventually result in shorting between adjacent metal lines
10
and
12
, or could at least result in undesirable stress in the portions of oxide layer
30
separating adjacent metal lines
10
and
12
.
It should also be noted that while the titanium and titanium nitride layers
16
,
18
, and
26
are hard enough to inhibit vertical distortion caused by stresses in main metal layer
20
, the portions of oxide layer
30
in between metal lines
10
and
12
are not sufficiently hard to inhibit stress-induced lateral distortion of metal layer
20
in metal lines
10
and
12
. Thus, for example, the oxide spacers sometimes found on the sidewalls of gate electrodes, do not serve to inhibit such stress-induced lateral distortion or expansion, but rather serve merely to provide insulation, or in some instances, temporary masking, e.g., during the formation of LDD regions in the underlying semiconductor substrate adjacent the channel region of an MOS device.
It would, therefore, be desirable to provide a structure which would result in inhibition of the lateral distortion of metal lines or other patterned metal formations in integrated circuit structures.
SUMMARY OF THE INVENTION
The invention comprises an integrated circuit structure having one or more metal lines thereon with metal line sidewall retention structures formed on the sides of metal lines comprising a material sufficiently hard to inhibit lateral distortion or expansion of portions of the metal line during subsequent processing or use of the metal line.
REFERENCES:
patent: 4980752 (1990-12-01), Jones, Jr.
patent: 5498555 (1996-03-01), Lin
patent: 5605858 (1997-02-01), Nishioka et al.
patent: 53-023562 (1978-04-01), None
patent: 60-124845 (1985-07-01), None
patent: 63-086453 (1988-04-01), None
Choudhury Ratan K.
Kapoor Ashok K.
Clark Sheila V.
LSI Logic Corporation
Taylor John P.
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