Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2002-09-26
2004-10-19
Cuneo, Kamand (Department: 2829)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S301000, C438S305000
Reexamination Certificate
active
06806149
ABSTRACT:
FIELD OF THE INVENTION
The invention is generally related to the field of MOSFET transistors and more specifically to a novel process to achieve a high active doping concentration and reduce the junction depth of the source and drain extension regions.
BACKGROUND OF THE INVENTION
Shown in
FIG. 1
is a cross-sectional diagram of a typical metal oxide semiconductor (MOS) transistor
5
. The MOS transistor
5
is fabricated in a semiconductor substrate
10
. The MOS transistor comprises a gate dielectric layer
20
that is formed on the surface of the substrate
10
. Typically this gate dielectric layer is formed using silicon oxide or nitrided silicon oxide although many other materials such as silicates have been used. The MOS transistor gate structure
30
is formed on the gate dielectric layer
20
and is typically formed using polycrystalline silicon. In addition to polycrystalline silicon other materials such as metals have been used to form the transistor gate. The combined dielectric layer/gate structure is often referred to as the gate stack. Following the formation of the transistor gate stack the source-drain extension regions
40
are formed using ion implantation. In forming these extension regions
40
dopants are implanted into the substrate using the gate stack as a mask. Therefore the extension regions
40
are aligned to the gate stack in what is known as the self-aligned process. Following the formation of the extension regions
40
, sidewall structures
50
are formed adjacent to the gate stack. These sidewall structures
50
are typically formed by depositing one or more conformal films on the surface of the substrate followed by an anisotropic etch process. This anisotropic etch will remove the conformal film[s] from all regions of the surface except those adjacent to gate stack structures. This results in the sidewall structures
50
shown in FIG.
1
. Following the formation of the sidewall structures the source and drain regions
60
are formed using ion implantation. The structure is then annealed at high temperature to activate the implanted dopant species in both the extension regions
40
and the source and drain regions
60
. During this high temperature anneal the dopants will diffuse into the semiconductor substrate. This dopant diffusion will result in a final junction depth of x
j
for the extension regions
40
.
As MOS transistor dimensions are reduced there is a need to achieve high dopant activation in the extension region
40
and simultaneously reduce the junction depth x
j
of the regions. Typically this is accomplished by trying to optimize the implantation dose and energy of the dopant species used to form the extension regions
40
. A reduction in X
j
often leads to an increase in the drain and source resistance of the MOS transistor resulting in a degrading of the MOS transistor performance. There is therefore a need to reduce the extension junction depth x
j
without sacrificing the active dopant concentration.
SUMMARY OF THE INVENTION
The instant invention describes a method for forming a MOS transistor using alkylsilane precursors during the sidewall formation process. In particular a gate stack is formed on a semiconductor substrate. In some embodiments an offset spacer structure is formed adjacent to said gate stack before forming extension regions in said semiconductor substrate adjacent to said gate stack. A carbon containing silicon oxide layer is then formed over the gate stack and the extension regions using alkylsilane precursors. Sidewall structures are then formed adjacent to said carbon containing silicon oxide layer on opposite sides of said gate stack. Source and drain regions are then formed in said semiconductor substrate adjacent to said sidewall structures and the entire structure is then thermally annealed.
Technical advantages of the instant invention include a reduction in transient enhanced diffusion, increased dopant activation, and a reduction in gate edge dopant depletion. Other technical advantages will be readily apparent to one skilled in the art from the following figures, description, and claims.
REFERENCES:
patent: 5989966 (1999-11-01), Huang
patent: 6153483 (2000-11-01), Yeh et al.
patent: 6406945 (2002-06-01), Lee et al.
patent: 6429062 (2002-08-01), Rubin
patent: 6461923 (2002-10-01), Hui et al.
Bevan Malcolm J.
Bu Haowen
Brady III W. James
Cuneo Kamand
Geyer Scott B.
McLarty Peter K.
Telecky , Jr. Frederick J.
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