Short turn around time mask ROM process

Details Short turn around time mask ROM process Short turn around time mask ROM process

1996-11-18

2000-04-25

Chang, Joni

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438276, H01L 218234

Patent

active

060543531

ABSTRACT:
A mask ROM stores information by selecting the work function of the gates of each FET in an array of FETs at a late stage in the manufacture of the ROM. The polysilicon gates of some of the FETs are doped N-type and the gates of the other FETs are doped P-type to form gates having different work functions, thereby forming FETs having different threshold voltages. The ROM consists of a parallel array of buried N.sup.+ bit lines formed in the substrate, a gate oxide layer deposited over the bit lines and a layer of polysilicon deposited on the gate oxide. The polysilicon is blanket doped N-type, gate electrodes are defined by photolithography, and then self-aligned silicide layers are formed on the gate electrodes. An insulating layer is then formed over the gate electrodes. Programming of the ROM is accomplished by forming a mask on the insulating layer and then implanting ions through openings in the mask, through the insulating layer and the silicide layer, and into the polysilicon layer. The implantation converts individual gate electrodes from N-type to P-type to alter the threshold voltage of the selected transistors. Relatively few additional processing steps are needed after the programming to complete the ROM.

REFERENCES:
patent: 4811066 (1989-03-01), Pfiester et al.
patent: 5358887 (1994-10-01), Hong
patent: 5681772 (1997-10-01), Chen et al.

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