Static information storage and retrieval – Read/write circuit – Having particular data buffer or latch
Patent
1982-06-23
1984-09-25
Fears, Terrell W.
Static information storage and retrieval
Read/write circuit
Having particular data buffer or latch
365 78, G11C 1300
Patent
active
044738943
ABSTRACT:
For use in a packed nine-bit-byte data processing system, a shift circuit comprises a shifter for subjecting a datum given by a bit sequence of nine-bit bytes to a shift of a preselected whole number N of digits or, more particularly, a shift of [9N/2] and [9(N-1)/2+5] bits when the whole number is an even and an odd integer, respectively. Before written in a register, the shifted bit sequence is edited by an editor into an edited bit sequence wherein each prescribed binary bit in each nine-bit byte is produced as it stands when the whole number is even and is placed, when the whole number is odd, at a next more significant bit than a four-bit byte which is next more significant in the shifted sequence than that binary bit.
REFERENCES:
patent: 4395764 (1983-07-01), Matsue
Fears Terrell W.
Nippon Electric Co. Ltd.
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