Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2007-03-21
2010-11-23
Thomas, Shane M (Department: 2186)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711S130000, C711S135000, C711SE12038, C711SE12039
Reexamination Certificate
active
07840759
ABSTRACT:
Methods and systems for shared cache eviction in a multi-core processing environment having a cache shared by a plurality of processor cores are provided. Embodiments include receiving from a processor core a request to load a cache line in the shared cache; determining whether the shared cache is full; determining whether a cache line is stored in the shared cache that has been accessed by fewer than all the processor cores sharing the cache if the shared cache is full; and evicting a cache line that has been accessed by fewer than all the processor cores sharing the cache if a cache line is stored in the shared cache that has been accessed by fewer than all the processor cores sharing the cache.
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Kornegay Marcus L.
Pham Ngan
Ahmed Hamdy S
Biggers & Ohanian LLP.
International Business Machines - Corporation
Seal Cynthia G.
Spraggins H. Barrett
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