Shallow trench isolation stress adjuster for MOS transistor

Details Shallow trench isolation stress adjuster for MOS transistor Shallow trench isolation stress adjuster for MOS transistor

2009-06-22

2010-10-12

Nguyen, Thanh (Department: 2893)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S424000, C257SE21409, C257SE21546

Reexamination Certificate

active

07811893

ABSTRACT:
The present invention provides, in one embodiment, a method of manufacturing a metal oxide semiconductor (MOS) transistor (100). The method comprises forming an active area (105) in a substrate (115), wherein the active area (105) is bounded by an isolation structure (120). The method further includes placing at least one stress adjuster (130) adjacent the active area (105), wherein the stress adjuster (130) is positioned to modify a mobility of a majority carrier within a channel region (155) of the MOS transistor (100). Other embodiments of the present invention include a MOS transistor device (200) and a process (300) for constructing an integrated circuit.

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Stanley Wolf, “Silicon Processing for the VSLI Era”, vol. 4, Lattice Press 2000, p. 459.

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