Shallow trench isolation process using oxide deposition and...

Details Shallow trench isolation process using oxide deposition and... Shallow trench isolation process using oxide deposition and...

2005-11-08

2005-11-08

Blum, David S. (Department: 2813)

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

Grooved and refilled with deposited dielectric material

Reexamination Certificate

active

06962857

ABSTRACT:
A method of manufacturing an integrated circuit (IC) utilizes a shallow trench isolation (STI) technique. The shallow trench isolation technique is used in a strained silicon (SMOS) process. The liner for the trench is formed from a layer deposited in a low temperature process which reduces germanium outgassing. The low temperature process can be an LPCVD. An annealing step can be utilized to form the liner.

REFERENCES:
patent: 5254873 (1993-10-01), Poon et al.
patent: 5266813 (1993-11-01), Comfort et al.
patent: 5406111 (1995-04-01), Sun
patent: 5455194 (1995-10-01), Vasquez et al.
patent: 5668044 (1997-09-01), Ohno
patent: 5700712 (1997-12-01), Schwalke
patent: 5719085 (1998-02-01), Moon et al.
patent: 5793090 (1998-08-01), Gardner et al.
patent: 5837612 (1998-11-01), Ajuria et al.
patent: 6013937 (2000-01-01), Beintner et al.
patent: 6037238 (2000-03-01), Chang et al.
patent: 6074930 (2000-06-01), Cho et al.
patent: 6074931 (2000-06-01), Chang et al.
patent: 6080618 (2000-06-01), Bergner et al.
patent: 6080627 (2000-06-01), Fan et al.
patent: 6080637 (2000-06-01), Huang et al.
patent: 6087705 (2000-07-01), Gardner et al.
patent: 6107143 (2000-08-01), Park et al.
patent: 6136664 (2000-10-01), Economikos et al.
patent: 6146970 (2000-11-01), Witek et al.
patent: 6150212 (2000-11-01), Divakaruni et al.
patent: 6168961 (2001-01-01), Vaccari
patent: 6207531 (2001-03-01), Pen-Liang
patent: 6214696 (2001-04-01), Wu
patent: 6271143 (2001-08-01), Mendicino
patent: 6306722 (2001-10-01), Yang et al.
patent: 6391731 (2002-05-01), Chong et al.
patent: 6399512 (2002-06-01), Blosse et al.
patent: 6414364 (2002-07-01), Lane et al.
patent: 6426278 (2002-07-01), Nowak et al.
patent: 6456370 (2002-09-01), Ingles, Jr.
patent: 6468853 (2002-10-01), Balasubramanian et al.
patent: 6498383 (2002-12-01), Beyer et al.
patent: 6524931 (2003-02-01), Perera
patent: 6548261 (2003-04-01), Smith et al.
patent: 6548361 (2003-04-01), En et al.
patent: 6566228 (2003-05-01), Beintner et al.
patent: 6613646 (2003-09-01), Sahota et al.
patent: 6646322 (2003-11-01), Fitzgerald
patent: 6656749 (2003-12-01), Paton et al.
patent: 6673696 (2004-01-01), Arasnia et al.
patent: 6706581 (2004-03-01), Hou et al.
patent: 2002/0045312 (2002-04-01), Zheng et al.
patent: 2002/0098689 (2002-07-01), Chong et al.
patent: 2003/0049893 (2003-03-01), Currie et al.
patent: 2003/0139051 (2003-07-01), Andideh et al.
patent: 2004/0061161 (2004-04-01), Radens et al.
patent: 2004/0089914 (2004-05-01), Mouli et al.
patent: 0 245 622 (1987-11-01), None
patent: 2 254 731 (1992-10-01), None
patent: WO 02/095818 (2002-11-01), None
patent: WO 02/101818 (2002-12-01), None
Sorab K. Ghandhi VSLI Fabrication Principles John Wiley and sons 1983 pp. 422-423.
Stanley Wolf Silicon Prcessing for the VSLI Era vol. 1 Lattice Press 1986 pp. 57-58, 194.
International Search Report for PCT/US2004/000982, 4 pages.
U.S. Appl. No. 10/389,456, filed Mar. 14, 2003, entitled “Shallow Trench Isolation For Strained Silicon Processes” (26 pgs.).
U.S. Appl. No. 10/341,863, filed Jan. 14, 2003, entitled “Shallow Trench Isolation for Strained Silicon Processes” (26 pgs.).
U.S. Appl. No. 10/341,848, filed Jan. 14, 2003, entitled “Post Trench Fill Oxidation Process for Strained Silicon Processes” (17 pgs.).
Written Opinion of the International Searching Authority; International Application No. PCT/US2004/007464; International Filing Date Mar. 11, 2004; 6 pgs.
International Search Report; International Application No. PCT/US2004/007464; mailed Jan. 9, 2004; 3 pgs.
U.S. Appl. No. 10/620,194, filed Jul. 15, 2003, entitled Front Side Seal to Prevent Germanium Outgassing 22 pgs.)
Ohkubo, Satoshi; Tamura Yasuyuki; Sugino, Rinji; Nakanishi, Toshiro; Sugita, Yoshihiro; Awaji, Naoki and Takasaki, Kanetake; “High Quality Ultra-Thin (4nm) Gate Oxide by UV/03Surface Pre-Treatment of Native Oxide”; 1995 Symposium On VLSI Technology; Digest of Technical Papers; Jun. 6-8, 1995; Kyoto, Japan; 3 pgs.
Van Zant, Peter, “Microchip Fabrication”, McGraw Hill, 1977, pp. 31 and 39.
Vossen, John L. and Kern, Werner, “Thin Film Processes II”, Academic Press, 1991, p. 333.
Rim, K., Welser, J., Hoyt, J.L., and Gibbons, J.F., “Enhanced Hole Mobilities in Surface-channel Strained-Si p-MOSFETs”, 1995 International Electron Devices Meeting Technical Digest, 5 pages.
Welser, J., Hoyt, J.L., Takagi, S. and Gibbons, J.F., “Strain Dependence of the Performance Enhancment in Strained-Si n-MOSFETs”, 1994 International Electron Devices Meeting Technical Digest, San Francisco, Ca Dec. 11-14, 1994, 5 pages.

Affiliated with

Also associated with

Rating

Shallow trench isolation process using oxide deposition and... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Shallow trench isolation process using oxide deposition and..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Shallow trench isolation process using oxide deposition and... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3461122