Serialization of hardware and software debug data

Details Serialization of hardware and software debug data Serialization of hardware and software debug data

2007-02-28

2009-12-29

Chung, Phung M (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C037S003000

Reexamination Certificate

active

07640472

ABSTRACT:
An integrated circuit (IC) having a link layer that (1) simultaneously receives both hardware debug data from on-chip ASIC logic and software debug data from an on-chip programmable processor and (2) serializes the hardware and software debug data streams to generate one or more serialized debug data streams, e.g., containing both hardware and software debug data, for output to off-chip debug testing equipment to support debug testing of both the ASIC logic and the programmable processor. Cross triggering can be implemented on-chip to support simultaneous display of correlated hardware and software debug information on appropriate monitors. The present invention supports debug testing using external debug testing equipment that does not require a hardware logic analyzer.

REFERENCES:
patent: 6912675 (2005-06-01), Swoboda
patent: 6985848 (2006-01-01), Swoboda et al.
patent: 7426579 (2008-09-01), McDaniel
patent: 7475303 (2009-01-01), Edgar et al.
“CoreSight On-chip Debug and Trace Technology,” ARM, The Architecture for the Digital World, http://web.archive.org/web/20050307232333/http://www.arm.com/p..., Mar. 7, 2005, 2 pages.
“High Speed Serial Trace Port,” ARM, The Architecture for the Digital World, Sep. 24, 2005, pp. 1-4.

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