Serial input/output semiconductor memory including an output dat

Static information storage and retrieval – Read/write circuit – Having particular data buffer or latch

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Details

365221, 36518912, 365233, 36518909, 377 78, 377 67, G11C 1900, G11C 11407, G11C 11413

Patent

active

051989999

ABSTRACT:
A semiconductor memory has an output data latch circuit controlled in response to a clock signal shifted by a half period from a control clock input to n one-bit shift register stages. The memory device includes a plurality of read data latch circuits, as well as a plurality of write or address data latch circuits, coupled to the n one-bit shift register stages and to a plurality of selector or multiplexor circuits. A noise filter is inserted in a clock input supply path to the n one-bit shift register stages but is not inserted in a clock input supply path to the output data latch circuit.

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