Serial input/output memory with a high speed test device

Details Serial input/output memory with a high speed test device Serial input/output memory with a high speed test device

1992-04-21

1994-02-08

LaRoche, Eugene R.

Static information storage and retrieval

Read/write circuit

With shift register

365221, 365236, 365240, G11C 700, G11C 800

Patent

active

052854094

ABSTRACT:
A device for changing a frequency of an internal control clock for testing a chip, by incorporating a mode selection circuit (30) and a high voltage detection circuit (40) in a serial input/output memory. The mode selection circuit (30) is connected between two selected adjacent circuits C.sub.n-2, C.sub.n-1 among a plurality of frequency conversion circuits C.sub.1 . . . C.sub.n, for accessing selectively either a clock pulse CP.sub.n-2 from the frequency conversion circuit C.sub.n-2, arranged in front thereof or a system clock XSK, in dependence upon an internal voltage sense signal IV, IVB. The high voltage detection circuit (40) transmits the internal voltage sense signal to the mode selection circuit (30) by detecting a level of externally applied voltage XV. The internal control clock ICK provided by this device attains a period of T.sub.XSK .times.2.sup.n-M+1, wherein "M" is a number of the counter receiving the mode selection signals MS, MSB next to the mode selection circuit.

REFERENCES:
patent: 4873671 (1989-10-01), Kowshik et al.
patent: 5051995 (1991-09-01), Tobita

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