Serial I/O using JTAG TCK and TMS signals

Details Serial I/O using JTAG TCK and TMS signals Serial I/O using JTAG TCK and TMS signals

2011-03-29

2011-03-29

Britt, Cynthia (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S733000

Reexamination Certificate

active

07917822

ABSTRACT:
The present disclosure describes a novel method and apparatus of using the JTAG TAP's TMS and TCK terminals as a general purpose serial Input/Output (I/O) bus. According to the present disclosure, the TAP's TMS terminal is used as a clock signal and the TCK terminal is used as a bidirectional data signal to allow serial communication to occur between; (1) an IC and an external controller, (2) between a first and second IC, or (3) between a first and second core circuit within an IC.

REFERENCES:
patent: 6393081 (2002-05-01), Whetsel
patent: 6442092 (2002-08-01), Tomita
patent: 6829730 (2004-12-01), Nadeau-Dostie et al.
patent: 6934897 (2005-08-01), Mukherjee et al.
patent: 7404128 (2008-07-01), Whetsel
“IEEE Standard Test Access Port and Boundary-Scan Architecture,” IEEE Std 1149.1-2001, vol., No., pp. i-200, 2001 doi: 10.1109-IEEESTD.2001.92950.
Bhavsar, D.; , “A method for synchronizing IEEE 1149.1 test access port for chip level testability access,” VLSI Design, 1998. Proceedings., 1998 Eleventh International Conference on , vol., No., pp. 289-292, Jan. 4-7, 1998 doi: 10.1109/ICVD.1998.646620.

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