Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Patent
1999-05-26
2000-12-05
Baker, Stephen M.
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
3408252, G01R 313185
Patent
active
06158035&
ABSTRACT:
A serial scan path communication architecture includes a plurality of circuits (30), some of which may include a memory (36). A memory access controller (38) is included on circuits with a memory (36) such that serial data may be written to and written from the memories without having to repetitively cycle through multiple shift operations.
REFERENCES:
patent: 4366478 (1982-12-01), Masuda et al.
patent: 4638313 (1987-01-01), Sherwood, Jr. et al.
patent: 4694293 (1987-09-01), Sugiyama et al.
Ashmore, Jr. Benjamin H.
Whetsel, Jr. Lee Doyle
Baker Stephen M.
Bassuk Lawrence J.
Telecky Frederick J.
Texas Instruments Incorporated
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