Serial clock noise immunity in a semiconductor memory integrated

Details Serial clock noise immunity in a semiconductor memory integrated Serial clock noise immunity in a semiconductor memory integrated

1992-08-13

1993-12-28

LaRoche, Eugene R.

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

365221, 365233, 365194, G11C 700

Patent

active

052745910

ABSTRACT:
A semiconductor memory integrated circuit having a serial port is modified to improve noise immunity on the serial clock (SC) input. This may be achieved by locking out subsequent serial clock signals during a serial port operation. A serial clock lockout signal is derived from the serial timing chain and coupled to the serial clock input one-shot circuit, so as to disable the one-shot circuit beginning in response to an initial serial clock input signal. The serial clock lockout is released, i.e., the one-shot circuit is enabled, after a delay period sufficient for the output terminals to transition to valid states. Alternatively, the one-shot circuit may be replaced by a serial clock lockout latch. The serial clock input signal is gated to the serial clock latch only when a serial clock lockout signal provided by the serial clock lockout latch is not asserted. The serial clock latch output is fed back to the lockout latch for setting the lockout latch in response to an initial serial clock input signal while first ensuring an adequate pulse width for setting the clock latch. Timing of the lockout circuitry may further include providing an SDQ output model for modelling propagation delay in the output portion of the serial port.

REFERENCES:
patent: 4945516 (1990-07-01), Kashiyama
patent: 5018110 (1991-05-01), Sugiyama
patent: 5031150 (1991-07-01), Ohsawa
patent: 5117395 (1992-05-01), Hashimoto

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