Serial accessed semiconductor memory with reconfigurable shift r

Details Serial accessed semiconductor memory with reconfigurable shift r Serial accessed semiconductor memory with reconfigurable shift r

1987-06-25

1989-01-03

Fears, Terrell W.

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

365215, 365233, 365235, 340700, 340768, G11C 1140, G11C 1300

Patent

active

047962313

ABSTRACT:
A semiconductor memory is comprised of four arrays (10), (12), (14) and (16) that have the memory elements therein arranged in accordance with pixel positions on a display. The memory arrays have associated shift registers (34), (36), (38) and (40) which have data loaded in parallel and output in a serial format to the display. Each of the shift registers can be connected in a circulating fashion or a shift register of adjacent arrays can be cascaded. Switches (56), (58), (60) and (62) are provided for configuring the shift registers for either circulation or cascading of data. In the circulating mode, the input and output of the shift registers is multiplexed on one pin whereas in the cascaded configuration, one array receives a dedicated serial input and the other array in the cascaded pair outputs the serial output on a dedicated pin.

REFERENCES:
patent: 4683555 (1987-07-01), Pinkham

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