Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2005-06-15
2008-09-02
Kerveros, James C (Department: 2117)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S726000
Reexamination Certificate
active
07421634
ABSTRACT:
According to an aspect of present invention, modules designed to operate with different frequency in functional (normal) mode are tested using a sequential scan based technique at the respective frequencies. In one embodiment the interface logic connecting the two modules is tested for at-speed performance (i.e., the same speed at which the interface would be operated in functional mode during normal operation).
REFERENCES:
patent: 5909451 (1999-06-01), Lach et al.
patent: 6442722 (2002-08-01), Nadeau-Dostie et al.
Abraham Jais
Jain Sandeep
Krishnamoorthy Nikila
Puvvada Naga Satya Srikanth
Brady III Wade James
Kerveros James C
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
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