Static information storage and retrieval – Addressing – Plural blocks or banks
Patent
1990-12-17
1993-10-19
LaRoche, Eugene R.
Static information storage and retrieval
Addressing
Plural blocks or banks
365221, 365239, G11C 700, G11C 804
Patent
active
052552420
ABSTRACT:
A sequential memory (10) uses interleaved memories (12a-b) with associated output buffers (22a-b) accomplish high data rates. Data access control circuitry (18) and bank select circuitry (20) control the order in which the memory banks (12a-b) are written to and read from. Output buffer circuits (22a-b) allow a data word to be read instantaneously after it is written to the sequential memory (10).
REFERENCES:
patent: 3824562 (1974-07-01), Leibowitz et al.
patent: 4642797 (1987-02-01), Hoberman
patent: 4864543 (1989-09-01), Ward et al.
patent: 4888741 (1989-12-01), Malinowski
patent: 4922457 (1990-05-01), Mizukami
patent: 4954987 (1990-09-01), Auvinen et al.
patent: 5012408 (1991-04-01), Conroy
patent: 5027326 (1991-06-01), Jones
patent: 5029142 (1991-07-01), Ando
patent: 5036493 (1991-07-01), Nielsen
patent: 5084841 (1992-01-01), Williams et al.
IBM Technical Disclosure Bulletin, vol. 30, No. 12, May 1988, pp. 339-341, "Increasing Data Read Rate From Memories".
Patent Abstracts of Japan, vol. 9, No. 190, p. 378, Aug. 7, 1985 (Abstract of JP-A-60059433 (Fujitsu Limited) published Apr. 5, 1985).
Tai Jy-Der
Ward Morris D.
Williams Kenneth L.
Barndt B. Peter
Brady III W. James
Donaldson Richard L.
LaRoche Eugene R.
Texas Instruments Incorporated
LandOfFree
Sequential memory does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Sequential memory, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Sequential memory will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-1357714