Static information storage and retrieval – Systems using particular element – Ferroelectric
Reexamination Certificate
1999-09-01
2001-11-06
Dinh, Son T. (Department: 2824)
Static information storage and retrieval
Systems using particular element
Ferroelectric
C365S154000, C327S202000, C327S203000, C326S049000
Reexamination Certificate
active
06314016
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATION
The entire disclosure of Japanese Patent Application No. Hei 10-247991 filed on Sep. 2, 1998 including specification, claims, drawings and summary is incorporated herein by reference in its entirety.
BACKGROUND OF INVENTION
1. Field of the Invention
This invention relates to sequential circuits and similar circuits, more specifically to the sequential circuits and the like using ferroelectrics.
2. Description of the Related Art
Latch circuits and flip-flop circuits are known generally as sequential circuits. A flip-flop circuit
2
depicted in
FIG. 14
is an example of the conventional sequential circuit.
FIG. 15
is a timing chart for illustrating the operations of the flip-flop circuit
2
depicted in FIG.
14
. The flip-flop circuit
2
comprises a latch circuit
4
(serves as the master latch circuit) and another latch circuit
6
(serves as the slave latch circuit) both connected in series. The output of the latch circuit
4
is labeled as “PA” depicted in
FIG. 15
, that is an output PA shows a signal detected at a point PA shown in FIG.
14
.
The latch circuit
4
is turned into the latched-state while turning the latch circuit
6
into the unlatched-state when a clock-pulse Cp becomes “Low” state from “High” state (see FIG.
15
(
a
)). In this way, data corresponding to data Dn (the data provided currently) at the negative edge (High-to-low transition) of the clock pulse Cp (the signal detected at the point PA has a value equivalent to an inverted value of the data Dn) is latched in the latch circuit
4
while outputting the data Dn to an output terminal Q.
Subsequently, the latch circuit
4
is turned into the unlatched-state while turning the latch circuit
6
into the latched-state when a clock-pulse Cp becomes “High” state from “low” state (see FIG.
15
(
b
)). In this way, the data Dn is latched in the latch circuit
6
while outputting the data Dn again to the output terminal Q.
Thereafter, the latch circuit
4
is turned into the latched-state again while turning the latch circuit
6
into the unlatched-state when a clock-pulse Cp becomes “Low” state from “High” state (see FIG.
15
(
c
)). In this way, data corresponding to the data Dn+1 (the data provided subsequently) at the negative edge (high-to-low transition) of the clock pulse Cp (the signal detected at the point PA has a value equivalent to an inverted value of the data Dn) is latched in the latch circuit
4
while outputting the data Dn+1 to the output terminal Q.
As described above, the data thus latched can be outputted within a duration equivalent to one complete cycle of the clock pulse Cp by latching data at the negative edge of the clock pulse Cp as a result of using the flip-flop circuit
2
. Consequently, stable outputs without noises can be obtained.
Sequential processings having a high reliability can be performed by using a combination of a plurality of sequential circuits such as the flip-flop circuit
2
and combined circuits such as logical gates.
The conventional sequence circuit such as the flip-flop circuit
2
, however, has the following problems to be solved. Adequate voltages must be applied to the circuit all the time in order to hold the data being processed.
Data being processed under sequential processings and that stored in a memory is completely erased when the power supply is shut off by an accident. The data can not be recovered even after the recovery of the power supply. In order to recover the data into the original one just before the accident, another sequential processings must be performed again from its beginning. It consumes much time to perform the sequential processings for every accident, and the data erase cause lack of processing reliability.
SUMMARY OF THE INVENTION
It is an object of the present invention to overcome the above mentioned drawbacks on the sequential circuits such as the flip-flop circuit associated with the prior art, and to provide sequential circuits realizing nonvolatile sequential circuits capable of holding data even when the power supply thereof is shut off.
In accordance with characteristics of the present invention, there is provided sequential circuit having a gate portion for switching input data according to a gate control signal provided thereto, the sequential circuit outputting a signal corresponding to the input data as output data when the gate portion is in an ON-state, the sequential circuit holding input data which is inputted substantially at right before an OFF-state of the gate portion while outputting a signal corresponding to the input data held therein as output data when the gate portion is in the OFF-state, the sequential circuit comprises:
a ferroelectric memorizing portion connected to an output terminal of the gate portion and holding a polarization state corresponding to a signal provided to the output terminal.
In accordance with characteristics of the present invention, there is provided a complementary metal-oxide inverter circuit connecting a p-channel metal-oxide-semiconductor field effect transistor and an N-channel metal-oxide-semiconductor field effect type transistor in series,
wherein at least one of the transistors is formed of a ferroelectric transistor.
A word “ferroelectric memorizing portion” used in claims represents a portion which stores data by using hysteresis of ferroelectrics. In a concrete form, the ferroelectric memorizing portion includes a ferroelectric transistor and a ferroelectric capacitor, not only those, a circuit or equivalents combining these may be included.
Further, a word “a ferroelectric transistor” used in claims represents a transistor using ferroelectrics such as a transistor having a structure so called MFMIS and an MFS-structured transistor both of which will be described subsequently. In the preferred embodiments, transistors NT and PT shown in
FIG. 1
form the ferroelectric transistor.
While the novel features of the invention are set forth in a general fashion, both as to organization and content, the invention will be better understood and appreciated, along with other objects and features thereof from the following detailed description taken in conjunction with the drawings.
REFERENCES:
patent: 4809225 (1989-02-01), Dimmler et al.
patent: 5361224 (1994-11-01), Takasu
patent: 5535154 (1996-07-01), Kiyono
patent: 5901088 (1999-05-01), Kraus
patent: 5923184 (1999-07-01), Ooms et al.
patent: 6025735 (2000-02-01), Gardner et al.
Dinh Son T.
Merchant & Gould P.C.
Rohm & Co., Ltd.
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