Electrical computers and digital processing systems: support – Synchronization of clock or timing signals – data – or pulses
Reexamination Certificate
1999-11-03
2003-05-06
Lee, Thomas (Department: 2153)
Electrical computers and digital processing systems: support
Synchronization of clock or timing signals, data, or pulses
C713S400000, C713S502000
Reexamination Certificate
active
06560715
ABSTRACT:
BACKGROUND OF THE INVENTION
The invention relates to processor-controlled electronic systems requiring a number of synchronous actions based on a system clock.
When such actions must be triggered at a very high rate or at very precise times, the response times of the processors can become incompatible.
The invention finds one particular application in digital mobile radio terminals. The processor has to manage a number of tasks with weak real time constraints, for example tasks which concern the user interface. Other functions of the terminal require rapid action triggered at very precise times, for example functions which concern signal processing and control of the radio interface.
In this kind of application, one option is to use a hardware timebase which periodically signals to the processor the triggering times of dated actions. The processor is then invoked frequently, which reduces its performance in terms of power consumption and computing power.
This also complicates software management and development.
Another option is to use two processors, namely a standard microprocessor/microcontroller for management purposes, which is essentially responsible for slow asynchronous events (keyboard-display management, system interface, etc) and a signal processor coupled to a timebase for managing synchronous or dated events.
One object of the present invention is to propose a new architecture which simplifies the management of synchronous events in a system of the above kind.
SUMMARY OF THE INVENTION
The invention thus proposes a sequencer for triggering actions synchronous with a system clock in an electronic system comprising a management processor, a program memory and peripheral units. The sequencer comprises: an instruction register including a date field for containing an instruction execution date, an instruction code field and a data field, means for loading the instruction register from the program memory via a DMA channel, a comparator receiving a current date obtained from the system clock and the execution date contained in the date field of the instruction register, and a control logic unit for decoding the contents of the instruction code and data fields of the instruction register and triggering actions in the peripheral units as deduced from such decoding at the time the comparator shows that the current date has reached the execution date, without intervention by the management processor.
Synchronous actions with a strong real time constraint are the responsibility of the sequencer, which frees the processor from actions which are heavy consumers of CPU time so that it can devote itself to higher level tasks or go to a standby mode to save power. This facilitates the use of multitask management software or real time OS (operating system) software by reducing the rate of interrupts. The sequencer then serves as a “hardware real time OS”.
The sequencer also simplifies management of the system standby mode. Associated with a synchronous, and synchronizable, timebase, it performs actions which are synchronized at the system level.
The sharing of peripheral resources by the processor and the sequencer makes specifying, implementing, testing and using peripherals associated with the sequencer and the processor flexible.
The sequencer preferably includes a command register which is accessible to the management processor and which contains commands for initializing operation of the sequencer. After initialization, the sequencer program is executed incrementally. The command register can also contain information on the status of the sequencer.
The means for loading the instruction register advantageously comprise a base address register which can be written by the processor, an incremental address counter driven by the control logic unit, a summing unit receiving the base address and the incremental address, and a DMA controller for loading the instruction register with a dated instruction read in the program memory at an address supplied by the summing unit.
Various programs can therefore be established in advance, calls to those programs being specified by the processor supplying the base address.
Another aspect of the present invention relates to an integrated circuit comprising a management processor, a program memory, peripheral units, means for obtaining a system clock and a sequencer as defined hereinabove for triggering actions synchronous with the system clock in the peripheral units.
An integrated circuit of the above kind has been implemented in silicon for a mobile radio application and the increase in the area of the circuit due to the presence of the sequencer of the invention was found to be small (less than 2%).
REFERENCES:
patent: 5542061 (1996-07-01), Omata
patent: 5694542 (1997-12-01), Kopetz
patent: 6317593 (2001-11-01), Vossler
patent: 0 578 361 (1994-01-01), None
patent: 02285421 (1990-11-01), None
patent: WO 98/22872 (1998-05-01), None
Kwak S H, et al., “A 32-Bit Low Power RISC Core For Embedded Applications”, 1995 IEEE Tencon. IEEE Region Ten International Conference On Microelectronics and VLSI, Hong-Kong, Nov. 6-10, 1995, pp. 488-491.
Bourdillat Jean-Pierre
Richy Michel
Barqadle Yasin
EADS Defence and Security Networks
Lee Thomas
McCracken & Frank
LandOfFree
Sequencer of synchronous actions in a processor system, and... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Sequencer of synchronous actions in a processor system, and..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Sequencer of synchronous actions in a processor system, and... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3073656