Sequence-based verification method and system

Details Sequence-based verification method and system Sequence-based verification method and system

2005-04-12

2005-04-12

Lamarre, Guy J. (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S819000, C716S030000

Reexamination Certificate

active

06880120

ABSTRACT:
A hardware verification method includes obtaining a set of packets to be driven by a device under test and obtaining a set of timing and relation criteria which determines a sequence in which the packets should be driven by the device under test. The method further includes starting multiple drive loops, each drive loop picking up a packet and forcing the device under test to drive the packet. The method further includes starting multiple expect loops, each expect loop determining when to expect a packet driven by the device under test and picking up the expected packet when it arrives. For each drive loop, the method confirms that the timing and relation criteria are satisfied prior to allowing the drive loop to force the device under test. For each expect loop, the method checks if the expected packet arrives within a specified time period and raises an error flag if the expected packet does not arrive within the specified time period.

REFERENCES:
patent: 5937182 (1999-08-01), Allingham
patent: 5958035 (1999-09-01), Carter et al.
patent: 6073194 (2000-06-01), Lowe
patent: 6154801 (2000-11-01), Lowe et al.
patent: 6324665 (2001-11-01), Fay
patent: 6370493 (2002-04-01), Knapp et al.

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