Separation of debug windows by IDS bit

Details Separation of debug windows by IDS bit Separation of debug windows by IDS bit

2005-12-27

2005-12-27

Beausoliel, Robert (Department: 2113)

Error detection/correction and fault detection/recovery

Data processing system error or fault handling

Reliability and availability

C710S260000

Reexamination Certificate

active

06981178

ABSTRACT:
A central processing unit that enables real time interrupts during a debug halt stores an interrupt during debug bit corresponding to the return address upon detection of an interrupt. The interrupt during debug bit has a first digital state if the central processing unit is in a debug halt state and a second digital state if the central processing unit is not in a debug halt state. Upon return from an interrupt the central processing unit enter a debug halt state if the interrupt during debug bit has the first state. The return address and the interrupt during debug bit can be embodied in a push-pop stack. The interrupt during debug bit register can be an unused least significant bit of the return address.

REFERENCES:
patent: 6249881 (2001-06-01), Porten et al.
patent: 6324684 (2001-11-01), Matt et al.
patent: 6557116 (2003-04-01), Swoboda et al.
patent: 6732298 (2004-05-01), Murthy et al.

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