Separate page table base address for minivisor

Details Separate page table base address for minivisor Separate page table base address for minivisor

2008-11-18

2011-12-13

Elmore, Reba I. (Department: 2189)

Electrical computers and digital processing systems: memory

Addressing combined with specific memory configuration or...

Virtual machine memory addressing

C711S207000

Reexamination Certificate

active

08078792

ABSTRACT:
In one embodiment, a processor supports an alternate address space during execution of non-guest code (such as a minivisor or a virtual machine monitor (VMM)). The alternate address space may be the guest address space. An instruction in the minivisor/VMM may specify the alternate address space for a data access, permitting the minivisor/VMM to read guest memory state via the alternate address space. In another embodiment, a processor may implement a page table base address register dedicated for the minivisor's use. In still another embodiment, the minivisor may be implemented as a specified entry point in the VMM address space.

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