Sense line termination circuit for semiconductor memory systems

Details Sense line termination circuit for semiconductor memory systems Sense line termination circuit for semiconductor memory systems

1978-11-16

1980-03-25

Fears, Terrell W.

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

365 78, 307238, G11C 1140

Patent

active

041953568

ABSTRACT:
A sense line termination circuit is provided intercoupled between a sense line of a plurality of static memory cells and a supply bus of high pull-up voltage to provide fast access to the memory cells with limited medium power dissipation. The termination circuit functions to pull up the sense line toward a predetermined intermediate high voltage value (which is about one threshold voltage Vt below the high pull-up voltage) when no memory cell has a low voltage memory node coupled to the sense line. The sense line termination circuit limits the voltage excursion of the sense lines and also permits the sense line to be pulled down with predetermined current limitation to a low voltage value when the sense line is coupled to a low voltage memory node. In a preferred embodiment, the sense line termination circuit comprises an enhancement mode FET device whose drain and gate are connected to the supply bus and whose source is connected in series with the drain of a depletion mode FET device whose source is connected to the sense line and whose gate may be connected to the same sense line or to other suitable gate bias voltage sources. The enhancement device has a substantially constant voltage drop across it from the pull-up supply voltage to the intermediate voltage, and substantially all the voltage variations between pull-up and pull-down occur across the depletion device. The enhancement device is preferably substantially larger in size and current carrying capacity than its corresponding depletion device.

REFERENCES:
patent: 3795898 (1974-03-01), Metha et al.

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