Sense amplifier/write circuit for semiconductor memories

Details Sense amplifier/write circuit for semiconductor memories Sense amplifier/write circuit for semiconductor memories

1986-07-08

1988-05-03

Hecker, Stuart N.

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

365208, 365179, 365212, G11C 700

Patent

active

047424885

ABSTRACT:
An adjustable sense amplifier circuit for read/write control of solid state memory devices is described. In a write mode the circuit includes a write select path, coupled to a current source and coupled to a differential pair of data select transistors, wherein the input data state sets each of two differential pairs formed by the memory element cross-coupled latch, such that the memory element stores selected data. In a sense mode, a second current path is selected wherein an adjustable sense level is provided to each of two differential pairs formed by the memory element. The current source is coupled to a reference voltage source which is independent of the supply voltage. The reference voltage source tracks changes in temperature and also provides low beta compensation for current loss due to the low beta value of transistors in the write and sense paths.

REFERENCES:
patent: 3622799 (1971-11-01), Marley et al.
patent: 4099070 (1978-07-01), Reinert
patent: 4272811 (1981-06-01), Wong
patent: 4459686 (1984-07-01), Toyoda

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