Sense amplifier of semiconductor memory device

Details Sense amplifier of semiconductor memory device Sense amplifier of semiconductor memory device

2000-08-23

2001-11-20

Elms, Richard (Department: 2824)

Static information storage and retrieval

Read/write circuit

Including level shift or pull-up circuit

C365S205000

Reexamination Certificate

active

06320798

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a sense amplifier of a semiconductor memory device.
2. Description of the Related Art
A semiconductor memory device circuit such as a dynamic random access memory (DRAM) uses a sense amplifier to read data from a memory cell or to refresh data in the memory cell.
FIG. 1
is a circuit diagram showing a conventional sense amplifier. In
FIG. 1
, the sense amplifier includes a pull-up sense amplifier
102
and a pull-down sense amplifier
104
. The pull-up sense amplifier
102
includes PMOS transistors mp
0
and mp
1
, and the pull-down sense amplifier
104
includes NMOS transistors mn
0
and mn
1
. The MOS transistors mp
1
and mp
0
(and mn
1
and mn
0
) are connected in series between a bit line BL and a complementary bit line BLB and have gates respectively coupled to the bit line BL and the complementary bit line BLB. The sense amplifier also includes a pull-up sense driver
106
and a pull-down driver
108
that provide and absorb electric charge from the lines BL and BLB via the pull-up sense amplifier
102
and the pull-down sense amplifier
104
, respectively. In this sense amplifier, the pull-up sense driver
106
is a PMOS transistor connected between a supply voltage Vdd and a node between PMOS transistors mp
0
and mp
1
, and the pull-down sense driver
108
is an NMOS transistor connected between ground and a node between NMOS transistors mn
0
and mn
1
. The pull-up sense driver
106
and the pull-down sense driver
108
operate as a current source and a current sink, respectively.
FIG. 2
shows a control circuit for generating a signal LAPG and a signal LANG, which respectively operate the pull-up sense driver
106
and the pull-down sense driver
108
shown in FIG.
1
. The control circuit of
FIG. 2
includes a NAND gate
202
and three inverters
204
,
206
, and
208
. When both input signals PS and PBLSIJ to the NAND gate
202
are in a “high” state, the output signal from the NAND gate
202
is in a “low” state. Accordingly, the signal LANG, which is the output of a first inverter
204
, is in a “high” state, and the signal LAPG, which is the output of a third inverter
208
, is in a “low” state. When signals PS and PBLSIJ are in the “high” state, the signal LANG turns on the pull-down sense driver
108
, and the signal LAPG turns on the pull-up sense driver
106
for a sensing operation in the circuit of FIG.
1
.
As illustrated in
FIG. 1
, the conventional sense amplifier uses a PMOS transistor as the pull-up sense driver
106
for providing electric charge to a line LA, and uses an NMOS transistor as the pull-down sense driver
108
for absorbing electric charge from a line LAB.
Sense amplifies such as in
FIG. 1
must be adapted as the capacity of memory cell arrays increases. For example, conventional memory cell arrays were 128 Kbits in capacity, but are now increasing to 192 Kbits or 256 Kbits to decrease the chip size of semiconductor devices. As the capacities of memory arrays increase, bit lines are becoming thinner and longer, which increases the resistance and capacitance of the bit lines. The driving capability of the pull-up sense driver
106
and the pull-down sense driver
108
must correspondingly increase with the array capacity. Additionally, PMOS transistors respond to an activation signal more slowly than would an NMOS transistor of the same size. Accordingly, to equalize the response of the pull-up sense driver
106
(realized by a PMOS transistor) with that of the pull-down sense driver
108
(realized by the NMOS transistor), the width of the PMOS transistor needs to be larger than that of the NMOS transistor. However, the larger PMOS transistors (being present in all of the sense amplifiers of the memory) increase chip size and reduce the advantage obtained from a larger capacity memory cell array.
SUMMARY OF THE INVENTION
An embodiment of the present invention provides a sense amplifier that is small and has an increased driving capability and thereby permits reduction of the chip size of memory devices employing the sense amplifier.
One embodiment of the invention is a sense amplifier including a pull-up sense amplifier, a pull-down sense amplifier, a pull-up sense driver, and a pull-down sense driver. The pull-up and pull-down sense amplifiers sense the data of a memory cell and are connected between a bit line and a complementary bit line. The pull-up sense driver includes an NMOS transistor that provides the pull-up sense amplifier with electric charge, and a pull-down sense driver includes an NMOS transistor that absorbs electric charge from the pull-down sense amplifier. The two NMOS transistors can be of the same dimensions, which reduces the chip area conventionally required for a larger PMOS transistor in the pull-up sense driver.
In the sense amplifier, the electric potential of a signal which drives the pull-up sense driver is preferably higher than that of a signal which drives the pull-down sense driver and/or higher than a supply voltage for the pull-up sense driver.


REFERENCES:
patent: 5491435 (1996-02-01), Mun et al.
patent: 5544110 (1996-08-01), Yuh
patent: 5638333 (1997-06-01), Lee
patent: 5646900 (1997-07-01), Tsukude et al.

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