Sense amplifier for integrated circuit memory devices having boo

Details Sense amplifier for integrated circuit memory devices having boo Sense amplifier for integrated circuit memory devices having boo

1996-08-23

1997-12-23

Nelms, David C.

Static information storage and retrieval

Read/write circuit

Flip-flop used for sensing

365190, 365222, 365202, 365233, G11C 706

Patent

active

057012687

ABSTRACT:
Integrated circuit memory devices include at least first and second memory cells electrically coupled to respective first and second sense bit signal lines of a sense amplifier. The sense amplifier comprises a circuit for amplifying a difference in potential between the first and second sense bit signal lines by driving these lines to respective first and second different potentials. A driving circuit is also provided for simultaneously driving the first and second sense bit signal lines towards the first potential in response to application of a boost control signal. This driving circuit preferably comprises a first capacitor electrically connected in series between the boost control input and the first sense bit signal line and a second capacitor electrically connected in series between the boost control input and the second sense bit signal line. The boost control signal is established at the first potential to drive both the sense bit signal lines from different intermediate potentials (e.g., 1/2VCC+, 1/2VCC) towards the first potential, prior to amplification of the difference in potential between the first and second sense bit signal lines by the sense amplifier. The present invention enables the sense amplifier to operate in an environment where the power supply voltage (e.g., VCC) is reduced and the different intermediate potentials (e.g., 1/2VCC+, 1/2VCC) to be amplified are initially established at potentials below the normal sensitivity of the sense amplifier.

REFERENCES:
patent: 4736343 (1988-04-01), Hidaka et al.
patent: 4803386 (1989-02-01), Kraus et al.
Koichiro Ishibashi et al., "A 12.5-ns 16Mb CMOS SRAM With Common-Centroid-Geometry-Layout Sense Amplifiers", IEEE Journal of Solid-State Circuits, vol. 29, No. 4, Apr. 1994, pp. 411-418.

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